Commits · d8888e14a0fcde1424c86cfc48a567379c80ac01 · Roger Ferrer / llvm-epi · GitLab

Jul 16, 2022
- Revert rG14364200821f7b2d97edf6e78160c514800d3ec6 "[ARM] Regenerate reg_sequence.ll test checks" · d8888e14
  Simon Pilgrim authored Jul 16, 2022
  d8888e14
- [SystemZ] Add funnel shift test coverage · bba0c0df
  Simon Pilgrim authored Jul 16, 2022
  bba0c0df
- [ARM] Regenerate reg_sequence.ll test checks · 14364200
  Simon Pilgrim authored Jul 16, 2022
  
  14364200
- [AArch64] Regenerate arm64-vector-ldst.ll test checks · dc681bc2
  Simon Pilgrim authored Jul 16, 2022
  
  dc681bc2
- [AArch64] Regenerate arm64-neon-simd-ldst-one.ll test checks · 2d4c43d4
  Simon Pilgrim authored Jul 16, 2022
  
  2d4c43d4
- [AArch64] Regenerate arm64-vmax.ll test checks · f7a9c5c6
  Simon Pilgrim authored Jul 16, 2022
  
  f7a9c5c6
- [AArch64] Regenerate arm64-mul.ll test checks · ccc2a60b
  Simon Pilgrim authored Jul 16, 2022
  
  ccc2a60b
- [DAG] Canonicalize non-inlane shuffle -> AND if all non-inlane referenced elements are known zero · a5d0122f
  Simon Pilgrim authored Jul 16, 2022
  a5d0122f
- [DAG] combineShiftAnd1ToBitTest - match "and (srl (not X), C)), 1 --> (and X, 1<<C) == 0" patterns · 1cb7416e
  Simon Pilgrim authored Jul 16, 2022
  1cb7416e
- [SDAG] Add test for DAGCombiner multiple result commutative CSE · dcfaaef1
  Itay Bookstein authored Jul 15, 2022
  dcfaaef1
- [X86][FP16] Enable vector support for FP16 emulation · f1879481
  Phoebe Wang authored Jul 16, 2022
  f1879481
Jul 15, 2022
- [LSR] Allow already invariant operand for ICmpZero matching [try 2] · 6ab686eb
  Philip Reames authored Jul 15, 2022
  6ab686eb
- [AMDGPU] Add remarks to output some resource usage · 67357739
  Vang Thao authored Mar 11, 2022
  67357739
- Revert "[LSR] Allow already invariant operand for ICmpZero matching" · 6fe766be
  Philip Reames authored Jul 15, 2022
  6fe766be
- [LSR] Allow already invariant operand for ICmpZero matching · 9153515a
  Philip Reames authored Jul 15, 2022
  9153515a
- [X86] test-vs-bittest.ll - add test coverage for (and (srl (not x), c), 1) patterns · 165eaf18
  Simon Pilgrim authored Jul 15, 2022
  165eaf18
- [ARM] Regenerate pr36577.ll test checks · 8dbf9e8d
  Simon Pilgrim authored Jul 15, 2022
  
  8dbf9e8d
- [AArch64] Regenerate optimize-imm.ll test checks · 95440c39
  Simon Pilgrim authored Jul 15, 2022
  
  95440c39
- [DAG] Move "xor (X logical_shift ShiftC), XorC --> (not X) logical_shift... · 3c8bf296
  Simon Pilgrim authored Jul 15, 2022
  3c8bf296
- [stackmaps] Legalise patchpoint arguments. · 2e62a26f
  Edd Barrett authored Jul 15, 2022
  2e62a26f
- [ARM] Regenerate hoist-and-by-const-from-shl-in-eqcmp-zero.ll · 0a9752d9
  Simon Pilgrim authored Jul 15, 2022
  0a9752d9
- [IR] Don't use blockaddresses as callbr arguments · 2a721374
  Nikita Popov authored Jul 07, 2022
  2a721374
- [X86] Use generic tuning for "x86-64" if "tune-cpu" is not specified · 190518da
  Phoebe Wang authored Jul 15, 2022
  190518da
- [RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel. · 79016f6e
  Craig Topper authored Jul 14, 2022
  79016f6e
- [AMDGPU] Fix for the test failure caused by the 2e29b013 · 65abc3a8
  Alexander Timofeev authored Jul 15, 2022
  65abc3a8
- [AMDGPU] Update the mechanism used to check for cycles and add eges in power-sched mutation · 8a12f20e
  jeff authored Jul 13, 2022
  
  8a12f20e
- [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. · dcfc1fd2
  Craig Topper authored Jul 14, 2022
  dcfc1fd2
- [RISCV] Add additional tests for D121833. NFC · 450f0bd1
  Craig Topper authored Jul 11, 2022
  
  450f0bd1
Jul 14, 2022
- [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable. · 2e29b013
  Alexander Timofeev authored Jun 21, 2022
  2e29b013
- [GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT. · d4f84df0
  Amara Emerson authored Jul 14, 2022
  d4f84df0
- [RISCV] Add a RISCV specific CodeGenPrepare pass. · 1a8468ba
  Craig Topper authored Jul 14, 2022
  1a8468ba
- [MachineCombiner] Don't compute the latency of transient instructions · 2f11b3a6
  Guozhi Wei authored Jul 14, 2022
  2f11b3a6
- [RISCV] Disable subregister liveness by default · d1a5669f
  Fraser Cormack authored Jul 13, 2022
  d1a5669f
- Revert "[StructurizeCFG] Improve basic block ordering" · c945d88d
  Brendon Cahoon authored Jul 14, 2022
  c945d88d
- [RISCV] Add a test showing a miscompilation with subreg liveness · 3b334978
  Fraser Cormack authored Jul 13, 2022
  3b334978
- [NFC][SVE] Add tests for zext(cmpeq(x, splat(0))) · a2fe6aa9
  Cullen Rhodes authored Jul 14, 2022
  a2fe6aa9
- [LoongArch] Implement OR combination to generate bstrins.w/d · 9b87ad33
  Weining Lu authored Jul 13, 2022
  9b87ad33
- [GlobalISel] Re-generate some checks. · cef349a3
  Amara Emerson authored Jul 14, 2022
  
  cef349a3
- [BPF] Handle anon record for CO-RE relocations · 6e6c1efe
  Yonghong Song authored Jul 12, 2022
  6e6c1efe
Jul 13, 2022
- [GlobalISel] Fix and(load)->zextload combine crash. · 2824bdd9
  Amara Emerson authored Jul 13, 2022
  2824bdd9