Commits · d8c817a9cdf478b21462101e603b0ad0e91f024a · Roger Ferrer / llvm-epi · GitLab

Jul 15, 2022
- [RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel. · 79016f6e
  Craig Topper authored Jul 14, 2022
  79016f6e
- [RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst. · bc0d6565
  Craig Topper authored Jul 14, 2022
  bc0d6565
- [AMDGPU] Update the mechanism used to check for cycles and add eges in power-sched mutation · 8a12f20e
  jeff authored Jul 13, 2022
  
  8a12f20e
- [RISCV] Make TuneSiFive7 depend on TuneNoDefaultUnroll instead of listing it for every SiFive7 CPU · 9913ea49
  Craig Topper authored Jul 14, 2022
  
  9913ea49
Jul 14, 2022
- [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable. · 2e29b013
  Alexander Timofeev authored Jun 21, 2022
  2e29b013
- [RISCV] Add a RISCV specific CodeGenPrepare pass. · 1a8468ba
  Craig Topper authored Jul 14, 2022
  1a8468ba
- [RISCV] Disable subregister liveness by default · d1a5669f
  Fraser Cormack authored Jul 13, 2022
  d1a5669f
- [SCEVExpander] Make CanonicalMode handing in isSafeToExpand() more robust (PR50506) · dcf4b733
  Nikita Popov authored Jul 13, 2022
  dcf4b733
- [AMDGPU] Update LiveVariables after killing an immediate def · e45aa230
  Jay Foad authored Jul 13, 2022
  e45aa230
- [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex · 055b409c
  Cullen Rhodes authored Jul 13, 2022
  055b409c
- [LoongArch] Implement OR combination to generate bstrins.w/d · 9b87ad33
  Weining Lu authored Jul 13, 2022
  9b87ad33
- [CodeGen] Move instruction predicate verification to emitInstruction · 3e0bf1c7
  David Green authored Jul 14, 2022
  3e0bf1c7
- [AMDGPU] SIMachineScheduler: Add support for several MachineScheduler features · e5c4cde4
  Jannik Silvanus authored May 20, 2022
  e5c4cde4
- [llvm] Use value instead of getValue (NFC) · 611ffcf4
  Kazu Hirata authored Jul 13, 2022
  
  611ffcf4
- [llvm] Make lib/Target/BPF/BTF.h self-contained · 18a910df
  owenca authored Jul 13, 2022
  
  18a910df
- [CSKY] Fix the br target operand type in td · 033324db
  Zi Xuan Wu (Zeson) authored Jul 14, 2022
  033324db
- [BPF] Handle anon record for CO-RE relocations · 6e6c1efe
  Yonghong Song authored Jul 12, 2022
  6e6c1efe
Jul 13, 2022
- [RISCV] Fold (sra (sext_inreg (shl X, C1), i32), C2) -> (sra (shl X, C1+32), C2+32). · 25775553
  Craig Topper authored Jul 13, 2022
  25775553
- [RISCV] Exploit fact that vscale is always power of two to replace urem sequence · dde2a7fb
  Philip Reames authored Jul 12, 2022
  dde2a7fb
- Revert "Move instruction predicate verification to emitInstruction" · 95252133
  David Green authored Jul 13, 2022
  95252133
- Move instruction predicate verification to emitInstruction · e2fb8c0f
  David Green authored Jul 13, 2022
  e2fb8c0f
- [AArch64][SVE] Prefer SIMD&FP variant of clast[ab] · 7c3cda55
  Cullen Rhodes authored Jul 08, 2022
  7c3cda55
- [RISCV] Add early-exit to RVV stack computation. NFCI. · b336cf85
  Fraser Cormack authored Jul 13, 2022
  b336cf85
- [LoongArch] Add codegen support for atomic fence, atomic load and atomic store · 47f3dc6d
  gonglingqin authored Jul 13, 2022
  47f3dc6d
- [LoongArch] Add codegen support for converting between unsigned integer and floating-point · e147a0f6
  gonglingqin authored Jul 13, 2022
  e147a0f6
- [LoongArch] Add codegen support for fpround, fpextend and converting between... · 1df96ce5
  gonglingqin authored Jul 13, 2022
  1df96ce5
- [RISCV] Add scheduling resources for vector segment instructions. · 2b045324
  Monk Chiang authored Jun 29, 2022
  2b045324
Jul 12, 2022
- [X86] Move isInRange(ArrayRef<int>) inside assert to fix NDEBUG builds. NFC. · 66bfd1ba
  Simon Pilgrim authored Jul 12, 2022
  66bfd1ba
- [X86] initial -mfunction-return=thunk-extern support · 2240d72f
  Nick Desaulniers authored Jul 12, 2022
  2240d72f
- [AMDGPU] SILowerControlFlow uses LiveIntervals · 5d41fe07
  Jay Foad authored Jul 12, 2022
  5d41fe07
- [NVPTX] Add missing pass names · 9ff10a0d
  Igor Kudrin authored Jul 12, 2022
  9ff10a0d
- [AArch64][SVE] Ensure PTEST operands have type nxv16i1 · e5edc1b5
  Rosie Sumpter authored Jun 30, 2022
  e5edc1b5
- [RISCV] Use X0 in place of VLMaxSentinel in lowering. · c5be6a83
  Craig Topper authored Jul 11, 2022
  c5be6a83
- [X86] Support -mstack-protector-guard-symbol · a45dd3d8
  Xiang1 Zhang authored Jul 12, 2022
  a45dd3d8
- Revert "[X86] Support -mstack-protector-guard-symbol" · 64378621
  Xiang1 Zhang authored Jul 12, 2022
  64378621
- [X86] Support -mstack-protector-guard-symbol · efbaad1c
  Xiang1 Zhang authored Jul 08, 2022
  
  efbaad1c
- [RISCV] Use MVT for the argument to getMaskTypeFor. NFC · c3c17b16
  Craig Topper authored Jul 11, 2022
  c3c17b16
Jul 11, 2022
- [AMDGPU] Fix bitcast v4i64/v16i16 · 2bd8e74b
  Piotr Sobczak authored Jul 11, 2022
  2bd8e74b
- [RISCV] Remove doPeepholeLoadStoreADDI. · 759e5e00
  Craig Topper authored Jul 11, 2022
  759e5e00
- [RISCV] Move the custom isel for (add X, imm) into SelectAddrRegImm. · 907d923a
  Craig Topper authored Jul 11, 2022
  907d923a