Commits · d8d193d5e2331da86a436ce39e7adedf4a700015 · Roger Ferrer / llvm-epi · GitLab

Jan 25, 2019
- [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FD · 0092df06
  Alex Bradbury authored Jan 25, 2019
  0092df06
- [RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll · d760910d
  Alex Bradbury authored Jan 25, 2019
  d760910d
- Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI · 05a60643
  Ana Pazos authored Jan 25, 2019
  05a60643
- [RISCV][NFC] s/f32/f64 in double-arith.ll · c67515d5
  Alex Bradbury authored Jan 25, 2019
  c67515d5
- [RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines · 38c4ec31
  Alex Bradbury authored Jan 25, 2019
  38c4ec31
- [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M · 456d3798
  Alex Bradbury authored Jan 25, 2019
  456d3798
- [RISCV] Custom-legalise 32-bit variable shifts on RV64 · 299d690a
  Alex Bradbury authored Jan 25, 2019
  299d690a
Jan 22, 2019
- [RISCV] Quick fix for PR40333 · cd26560e
  Alex Bradbury authored Jan 22, 2019
  cd26560e
Jan 17, 2019
- [RISCV] Add codegen support for RV64A · 07f1c623
  Alex Bradbury authored Jan 17, 2019
  07f1c623
Jan 14, 2019
- Replace "no-frame-pointer-*" function attributes with "frame-pointer" · b7cef81f
  Francis Visoiu Mistrih authored Jan 14, 2019
  b7cef81f
Jan 12, 2019
- [RISCV] Introduce codegen patterns for RV64M-only instructions · 61aa9400
  Alex Bradbury authored Jan 12, 2019
  61aa9400
- [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions · d05eae7a
  Alex Bradbury authored Jan 12, 2019
  d05eae7a
Jan 11, 2019
- [RISCV][NFC] Add CHECK lines for atomic operations on RV64I · eea0b070
  Alex Bradbury authored Jan 11, 2019
  eea0b070
Dec 13, 2018
- [RISCV] Add support for the various RISC-V FMA instruction variants · 919f5fb8
  Alex Bradbury authored Dec 13, 2018
  919f5fb8
Dec 01, 2018
- [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases · 757d2962
  Alex Bradbury authored Dec 01, 2018
  757d2962
Nov 30, 2018
- [SelectionDAG] Support result type promotion for FLT_ROUNDS_ · fca95cfe
  Alex Bradbury authored Nov 30, 2018
  fca95cfe
- [SelectionDAG] Support promotion of PREFETCH operands · bd24c7b0
  Alex Bradbury authored Nov 30, 2018
  bd24c7b0
- [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands · 36e0fd1d
  Alex Bradbury authored Nov 30, 2018
  36e0fd1d
- [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V · e0e62e97
  Alex Bradbury authored Nov 30, 2018
  e0e62e97
- [RISCV] Introduce codegen patterns for instructions introduced in RV64I · bc96a98e
  Alex Bradbury authored Nov 30, 2018
  bc96a98e
Nov 29, 2018
- [RISCV] Implement codegen for cmpxchg on RV32IA · 66d9a752
  Alex Bradbury authored Nov 29, 2018
  66d9a752
Nov 16, 2018
- [RISCV] Constant materialisation for RV64I · 2146e8fb
  Alex Bradbury authored Nov 16, 2018
  2146e8fb
Nov 15, 2018
- [RISCV] Mark FREM as Expand · 77272404
  Alex Bradbury authored Nov 15, 2018
  77272404
Nov 12, 2018
- [RISCV] Support .option relax and .option norelax · 9c03e4ca
  Alex Bradbury authored Nov 12, 2018
  9c03e4ca
Nov 09, 2018
- [RISCV] Avoid unnecessary XOR for seteq/setne 0 · 1cc2d0b9
  Alex Bradbury authored Nov 09, 2018
  1cc2d0b9
- [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432 · a9da1de5
  Alex Bradbury authored Nov 09, 2018
  a9da1de5
Nov 02, 2018
- [RISCV] Add some missing expansions for floating-point intrinsics · 52c27785
  Alex Bradbury authored Nov 02, 2018
  52c27785
Oct 13, 2018
- [RISCV] Eliminate unnecessary masking of promoted shift amounts · 748d080e
  Alex Bradbury authored Oct 12, 2018
  748d080e
Oct 11, 2018
- [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142 · 686ef921
  Alex Bradbury authored Oct 11, 2018
  686ef921
Oct 08, 2018
- [RISCV] Update alu8.ll and alu16.ll test cases · 5af6c149
  Alex Bradbury authored Oct 08, 2018
  5af6c149
Oct 07, 2018
- [RISCV] Introduce alu8.ll and alu16.ll tests · 47afe5e7
  Alex Bradbury authored Oct 07, 2018
  47afe5e7
Oct 05, 2018
- [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default · 90fc1007
  Alex Bradbury authored Oct 05, 2018
  90fc1007
Oct 04, 2018
- [RISCV][NFC] Remove dead CHECK lines from vararg.ll test · a4b7b6da
  Alex Bradbury authored Oct 04, 2018
  a4b7b6da
- [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F · e96b7c88
  Alex Bradbury authored Oct 04, 2018
  e96b7c88
Oct 03, 2018
- [RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.ll · efceb598
  Alex Bradbury authored Oct 03, 2018
  efceb598
Sep 19, 2018
- [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A · 21aea51e
  Alex Bradbury authored Sep 19, 2018
  21aea51e
Aug 27, 2018
- [RISCV] atomic_store_nn have a different layout to regular store · fe282170
  Roger Ferrer Ibanez authored Aug 27, 2018
  fe282170
Aug 16, 2018
- [SelectionDAG] Improve the legalisation lowering of UMULO. · 73e8a784
  Eli Friedman authored Aug 16, 2018
  73e8a784
- [RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true · fdc4647c
  Alex Bradbury authored Aug 16, 2018
  fdc4647c
Jul 31, 2018
- [RISCV] Fixed test case failure due to r338047 · 2baa7674
  Ana Pazos authored Jul 31, 2018
  2baa7674