Commits · d8ec09c74f8096946df4680d3aed878c472c97a4 · Roger Ferrer / llvm-epi · GitLab

Oct 24, 2016
- [WebAssembly] Fix a broken URL. · 5d3391f8
  Dan Gohman authored Oct 24, 2016
  5d3391f8
- [WebAssembly] Define the `end` opcode value. · 4becc585
  Dan Gohman authored Oct 24, 2016
  4becc585
- [WebAssembly] Update opcode values according to recent spec changes. · c968297b
  Dan Gohman authored Oct 24, 2016
  c968297b
- [WebAssembly] Add an option to make get_local/set_local explicit. · 4fc4e42d
  Dan Gohman authored Oct 24, 2016
  4fc4e42d
- Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. · 6733564e
  Peter Collingbourne authored Oct 24, 2016
  6733564e
- Revert r284972 and remove other defaulted copy/move constructors/= · eb617240
  Krzysztof Parzyszek authored Oct 24, 2016
  eb617240
- [PPC] Generate positive FP zero using xor insn instead of loading from constant area · c90b02cf
  Ehsan Amiri authored Oct 24, 2016
  c90b02cf
- Revert r284580+r284917. ("Synthesize TBB/TBH instructions") · b37864b5
  Eli Friedman authored Oct 24, 2016
  b37864b5
- [AArch64] Optionally use the Newton series for reciprocal estimation · eff2bd9d
  Evandro Menezes authored Oct 24, 2016
  eff2bd9d
- [PPC] Better codegen for AND, ANY_EXT, SRL sequence · 1f31e915
  Ehsan Amiri authored Oct 24, 2016
  1f31e915
- AMDGPU: Fix Two Address problems with v_movreld · a785209b
  Nicolai Haehnle authored Oct 24, 2016
  a785209b
- Remove unused #includes of TimeValue.h. NFC. · 51c454c1
  Pavel Labath authored Oct 24, 2016
  51c454c1
- AArch64 ILP32 relocations for assembly and ELF · 504bf334
  Joel Jones authored Oct 24, 2016
  504bf334
- [RDF] Add default move constructors/assignment operators · f74683f9
  Krzysztof Parzyszek authored Oct 24, 2016
  f74683f9
- [mips] synci microMIPS instruction definition. · 9c348548
  Simon Dardis authored Oct 24, 2016
  9c348548
- [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR. · 8ec5c732
  Craig Topper authored Oct 24, 2016
  8ec5c732
Oct 23, 2016
- [X86][SSE] Add SSE41/AVX1 costs for vector shifts. · 6ac1e98b
  Simon Pilgrim authored Oct 23, 2016
  6ac1e98b
- Use APInt::isAllOnesValue instead of popcnt. NFCI. · 96ef0c11
  Simon Pilgrim authored Oct 23, 2016
  96ef0c11
- [AVR] Add the machine code disassembler · 479a13c0
  Dylan McKay authored Oct 22, 2016
  479a13c0
Oct 22, 2016
- [X86][AVX512VL] Added support for combining target 256-bit shuffles to AVX512VL VPERMV3 · d3829c89
  Simon Pilgrim authored Oct 22, 2016
  d3829c89
- [X86][AVX512] Added support for combining target shuffles to AVX512 VPERMV3 · 56c0524f
  Simon Pilgrim authored Oct 22, 2016
  56c0524f
- [ARM] Fix crash in ConstantIslands · 2bae8640
  James Molloy authored Oct 22, 2016
  2bae8640
- [X86] Add support for printing shuffle comments for VALIGN instructions. · b084c90a
  Craig Topper authored Oct 22, 2016
  b084c90a
- [X86] Add support for lowering v4i64 and v8i64 shuffles directly to PALIGNR. I... · 7b2b8db4
  Craig Topper authored Oct 22, 2016
  7b2b8db4
- [X86] Remove unnecessary AVX2 check that was already covered by an assertion... · 9f374533
  Craig Topper authored Oct 22, 2016
  9f374533
- [X86] Remove 128-bit lane handling from the main loop of... · bea5cb54
  Craig Topper authored Oct 22, 2016
  bea5cb54
- [X86][SSE] Use getConstVector helper for VPERMV mask generation. NFCI. · 0d376bcb
  Simon Pilgrim authored Oct 22, 2016
  0d376bcb
- [AMDGPU] Perform uchar to float combine for ISD::SINT_TO_FP · fda33eaf
  Konstantin Zhuravlyov authored Oct 21, 2016
  fda33eaf
Oct 21, 2016
- AMDGPU/SI: Fix crash caused by r284267 · 6c7dd980
  Tom Stellard authored Oct 21, 2016
  6c7dd980
- X86: Improve BT instruction selection for 64-bit values. · e9bd4982
  Peter Collingbourne authored Oct 21, 2016
  e9bd4982
- [X86][AVX512BWVL] Added support for lowering v16i16 shuffles to AVX512BWVL vpermw · ab488723
  Simon Pilgrim authored Oct 21, 2016
  ab488723
- [X86][AVX512BWVL] Added support for combining target v16i16 shuffles to AVX512BWVL vpermw · da814cba
  Simon Pilgrim authored Oct 21, 2016
  da814cba
- [X86][AVX512] Added support for combining target shuffles to AVX512... · 0109bf11
  Simon Pilgrim authored Oct 21, 2016
  0109bf11
- [RDF] Use RegisterId typedef more consistently, NFC · 6e7fa99d
  Krzysztof Parzyszek authored Oct 21, 2016
  6e7fa99d
- [Hexagon] Handle spills of partially defined double vector registers · b71085b5
  Krzysztof Parzyszek authored Oct 21, 2016
  b71085b5
- [WebAssembly] Fix for 0xc call_indirect changes · 6f69783f
  Derek Schuff authored Oct 21, 2016
  6f69783f
- Set the vectorizer MaxInterleaveFactor for Exynos. · 9daf8110
  Abderrazek Zaafrani authored Oct 21, 2016
  9daf8110
- [X86] Use DAG::getBuildVector helper wrapper where possible. NFCI. · 2d96daa8
  Simon Pilgrim authored Oct 21, 2016
  2d96daa8
- Test commit · 9f382f53
  Abderrazek Zaafrani authored Oct 21, 2016
  9f382f53
- [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. · 751985a7
  Artem Tamazov authored Oct 21, 2016
  751985a7