Commits · d9207d3f0bad15caefbb44f307e42862a755333b · Roger Ferrer / llvm-epi · GitLab

Feb 21, 2021
- [RISCV] Add test cases for add/sub/mul overflow intrinsics. NFC · d9207d3f
  Craig Topper authored Feb 21, 2021
  d9207d3f
Feb 20, 2021
- [RISCV] Add another test case showing failure to use remw when the RHS has... · 038bd147
  Craig Topper authored Feb 20, 2021
  038bd147
- [RISCV] Add an additional remw test to rv64m-exhaustive-w-insts.ll. NFC · 09966a66
  Craig Topper authored Feb 20, 2021
  09966a66
- [RISCV] Support extraction of misaligned subvectors · 3e1317fd
  Fraser Cormack authored Feb 18, 2021
  3e1317fd
- [RISCV] Improve register allocation around vector masks · 9aa20cae
  Fraser Cormack authored Feb 19, 2021
  9aa20cae
- [RISCV] Pre-commit test case for D97055. NFC. · 55b75d83
  Fraser Cormack authored Feb 20, 2021
  55b75d83
- [X86][SSE] Use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI. · ee0dee7d
  Simon Pilgrim authored Feb 20, 2021
  ee0dee7d
- [X86][SSE] vector-compare-combines.ll - use llvm min/max intrinsics instead of... · a274062b
  Simon Pilgrim authored Feb 20, 2021
  a274062b
- [X86][AVX] Remove AVX2 min/max intrinsics tests · 75e66b88
  Simon Pilgrim authored Feb 20, 2021
  75e66b88
- [X86][SSE] Remove SSE41 min/max intrinsics tests · b9f3b305
  Simon Pilgrim authored Feb 20, 2021
  b9f3b305
- [X86][SSE2] Remove SSE2 min/max intrinsics tests · 63422bcb
  Simon Pilgrim authored Feb 20, 2021
  63422bcb
- [X86] KnownBits - use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI. · ff51bcee
  Simon Pilgrim authored Feb 20, 2021
  ff51bcee
- [DAG] foldSubToUSubSat - fold sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit))) · 761bbed2
  Simon Pilgrim authored Feb 19, 2021
  761bbed2
- [AArch64][GlobalISel] Add selection support for G_VECREDUCE of <2 x i32> · 067ec53d
  Amara Emerson authored Feb 20, 2021
  067ec53d
Feb 19, 2021
- [AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal. · 27566e9c
  Amara Emerson authored Feb 19, 2021
  
  27566e9c
- [X86] Regenerate 2007-06-28-X86-64-isel.ll · d7350efc
  Simon Pilgrim authored Feb 19, 2021
  
  d7350efc
- [X86] Remove unused intrinsic declaration · 3dae0b57
  Simon Pilgrim authored Feb 19, 2021
  
  3dae0b57
- [X86] Regenerate 2011-12-06-AVXVectorExtractCombine.ll · 6ad4bf33
  Simon Pilgrim authored Feb 19, 2021
  
  6ad4bf33
- [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. · dbf910f0
  Craig Topper authored Feb 19, 2021
  dbf910f0
- [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 · 98dff5e8
  Craig Topper authored Feb 19, 2021
  98dff5e8
- [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner · 8d3442ed
  Jessica Paquette authored Feb 17, 2021
  8d3442ed
- [MemCopyOpt] Enable MemorySSA by default · 71a8e4e7
  Nikita Popov authored Jan 10, 2021
  71a8e4e7
- Make fixed-abi default for AMD HSA OS · 3c297a25
  madhur13490 authored Feb 10, 2021
  3c297a25
- [AMDGPU] Add some GFX9 test coverage. NFC. · b2c7f06d
  Jay Foad authored Feb 19, 2021
  
  b2c7f06d
- [DAG] visitTRUNCATE - attempt to truncate USUBSAT · 5d3930bb
  Simon Pilgrim authored Feb 19, 2021
  5d3930bb
- Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer" · 7a5c26e9
  David Green authored Feb 19, 2021
  7a5c26e9
- [X86][SSE] Add tests for trunc(usubsat()) patterns. · c1664c5a
  Simon Pilgrim authored Feb 19, 2021
  
  c1664c5a
- [AMDGPU] WQM/WWM: Fix marking of partial definitions · 8181dcd3
  Carl Ritson authored Feb 19, 2021
  8181dcd3
- [X86][AVX] getFauxShuffleMask - decode VBROADCAST(EXTRACT_VECTOR_ELT(V,0)) · 2258b367
  Simon Pilgrim authored Feb 19, 2021
  2258b367
- [X86] Fix a codegen crash in getSetCCResultType · c98644c2
  Wang, Pengfei authored Feb 19, 2021
  c98644c2
- [AArch64] Add some missing Neoverse features · 260f90bb
  Sjoerd Meijer authored Feb 18, 2021
  260f90bb
- [FPEnv][AArch64] Implement lowering of llvm.set.rounding · 2c4f60e4
  Serge Pavlov authored Feb 16, 2021
  2c4f60e4
- [RISCV] Remove redundant test cases for index segment store (8/8). · 0ab3558b
  Hsiangkai Wang authored Feb 19, 2021
  0ab3558b
- [RISCV] Remove redundant test cases for index segment store (7/8). · c2f27da7
  Hsiangkai Wang authored Feb 19, 2021
  c2f27da7
- [RISCV] Remove redundant test cases for index segment store (6/8). · b0168a38
  Hsiangkai Wang authored Feb 19, 2021
  b0168a38
- [RISCV] Remove redundant test cases for index segment store (5/8). · de6d640f
  Hsiangkai Wang authored Feb 19, 2021
  de6d640f
- [RISCV] Remove redundant test cases for index segment load (4/8). · 3b4b1c84
  Hsiangkai Wang authored Feb 19, 2021
  
  3b4b1c84
- [RISCV] Remove redundant test cases for index segment load (3/8). · 8cc0b1cb
  Hsiangkai Wang authored Feb 19, 2021
  8cc0b1cb
- [RISCV] Remove redundant test cases for index segment load (2/8). · 320250e4
  Hsiangkai Wang authored Feb 19, 2021
  
  320250e4
- [RISCV] Remove redundant test cases for index segment load (1/8). · a32c79ce
  Hsiangkai Wang authored Feb 19, 2021
  a32c79ce