Commits · d992950078efd81971b8d84a862671b17af88bff · Roger Ferrer / llvm-epi · GitLab

Sep 27, 2021
- [InstCombine] add tests for opposing shifts separated by trunc; NFC · d9929500
  Sanjay Patel authored Sep 27, 2021
  
  d9929500
- Bad SLPVectorization shufflevector replacement, resulting in write to wrong memory location · e27a6db5
  Jameson Nash authored Jul 22, 2021
  e27a6db5
- [AMDGPU] Change ASAN init/fini kernels linkage to external. · e90b512c
  Praveen Velliengiri authored Sep 27, 2021
  e90b512c
- [RISCV] Fold store of vmv.x.s to a vse with VL=1. · a2a07e8d
  Craig Topper authored Sep 27, 2021
  a2a07e8d
- [RISCV] Improve support for forming widening multiplies when one input is a scalar splat. · 933182e9
  Craig Topper authored Sep 27, 2021
  933182e9
- [NFC][AMDGPU] Update cost model tests: · 1f73f0c1
  Daniil Fukalov authored Sep 27, 2021
  1f73f0c1
- Fix tests defaulting to incorrect triples on AIX · 56049b71
  Jake Egan authored Sep 27, 2021
  56049b71
- [InstCombine] generalize fold for (trunc (X u>> C1)) u>> C · 21429cf4
  Sanjay Patel authored Sep 27, 2021
  21429cf4
- [AMDGPU] Ignore KILLs when forming clauses · bf980930
  Sebastian Neubauer authored Jul 16, 2021
  bf980930
- [FuncSpec] Don't specialise (or crash) on poison or constexpr values · eba76056
  Sjoerd Meijer authored Sep 27, 2021
  eba76056
- [AArch64] Fix neon-reverseshuffle test extension. NFC · ebee606e
  David Green authored Sep 27, 2021
  ebee606e
- [LoopFlatten] Precommit new test widen-iv2.ll for D110234. · a588ae48
  Sjoerd Meijer authored Sep 22, 2021
  
  a588ae48
- Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch... · 3a998c06
  Jun Ma authored Sep 27, 2021
  3a998c06
- [X86][Costmodel] Load/store i16 Stride=2 VF=32 interleaving costs · 7424deb7
  Roman Lebedev authored Sep 27, 2021
  7424deb7
- [X86][Costmodel] Load/store i16 Stride=2 VF=16 interleaving costs · a5113e94
  Roman Lebedev authored Sep 27, 2021
  a5113e94
- [X86][Costmodel] Load/store i16 Stride=2 VF=8 interleaving costs · 70c90cc5
  Roman Lebedev authored Sep 27, 2021
  70c90cc5
- [X86][Costmodel] Load/store i16 Stride=2 VF=4 interleaving costs · 49e532aa
  Roman Lebedev authored Sep 27, 2021
  49e532aa
- [DAGCombiner][VP] Fold zero-length or false-masked VP ops · e2b46e33
  Fraser Cormack authored Sep 01, 2021
  e2b46e33
- [ARM] Improve detection of fallthough when aligning blocks · bb2d23dc
  David Green authored Sep 27, 2021
  bb2d23dc
- [Test] Regenerate test checks with autogen script · 4992220e
  Max Kazantsev authored Sep 27, 2021
  
  4992220e
- [X86] combineVectorHADDSUB - remove the broken HOP(x,x) merging code (PR51974) · 468ff703
  Simon Pilgrim authored Sep 27, 2021
  468ff703
- [LV] Add tests where rt checks may make vectorization unprofitable. · 4b581e87
  Florian Hahn authored Sep 07, 2021
  4b581e87
- [AArch64][test] Add more tests of add/sub with immediate · 683e5063
  Ben Shi authored Sep 25, 2021
  683e5063
- [Test] Add test showing that SCEV cannot properly infer ranges of cycled phis · 0bd9162f
  Max Kazantsev authored Sep 27, 2021
  
  0bd9162f
- [X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16) · 902ec614
  Freddy Ye authored Sep 27, 2021
  902ec614
- [Test] Add some simple tests where IndVars cannot remove a check in loop · e787678c
  Max Kazantsev authored Sep 27, 2021
  e787678c
- [GlobalISel] Re-generate some call lowering tests with the new CHECK-NEXT behaviour. · acd13994
  Amara Emerson authored Sep 26, 2021
  
  acd13994
Sep 26, 2021
- [MCJIT] This test shouldn't require an unwind table. · daf0b2f0
  Lang Hames authored Sep 26, 2021
  daf0b2f0
- [X86][SSE] combineMulToPMADDWD - enable sext_extend_vector_inreg(vXi16) ->... · c0eff50f
  Simon Pilgrim authored Sep 26, 2021
  c0eff50f
- [X86] Fold PACK(*_EXTEND_VECTOR_INREG, UNDEF) -> *_EXTEND_VECTOR_INREG · ed3e4917
  Simon Pilgrim authored Sep 26, 2021
  ed3e4917
- [X86] Fold ADD(VPMADDWD(X,Y),VPMADDWD(Z,W)) -> VPMADDWD(SHUFFLE(X,Z), SHUFFLE(Y,W)) · 3fe97672
  Simon Pilgrim authored Sep 26, 2021
  3fe97672
- [X86][Costmodel] Load/store i16 VF=2 interleaving costs · d9413f46
  Roman Lebedev authored Sep 26, 2021
  d9413f46
- [InstCombine] move add after min/max intrinsic · 6063e6b4
  Sanjay Patel authored Sep 26, 2021
  6063e6b4
- [CostModel][X86] Improve AVX1/AVX2 v16i32->v16i16/v16i8 truncation costs (PR51972) · 3538ee76
  Simon Pilgrim authored Sep 26, 2021
  3538ee76
Sep 25, 2021
- [AA] Move earliest escape tracking from DSE to AA · ba664d90
  Nikita Popov authored Sep 23, 2021
  ba664d90
- [DSE] Make capture check more precise · 327bbbb1
  Nikita Popov authored Sep 25, 2021
  327bbbb1
- [DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116) · 18c8ed54
  Simon Pilgrim authored Sep 25, 2021
  18c8ed54
- [CostModel][X86] Adjust vXi32 multiply costs if it can be performed using PMADDWD · 8c83bd3b
  Simon Pilgrim authored Sep 25, 2021
  8c83bd3b
- [X86][SSE] combineMulToPMADDWD - mask off upper bits of sign-extended vXi32 constants · eb7c78c2
  Simon Pilgrim authored Sep 25, 2021
  eb7c78c2
- [X86][SSE] combineMulToPMADDWD - enable sext(v8i16) -> zext(v8i16) fold on sub-128 bit vectors · 2a4fa0c2
  Simon Pilgrim authored Sep 25, 2021
  
  2a4fa0c2