Commits · d9ae0788c432c718af146ffda9c2f6a0ee22007a · Roger Ferrer / llvm-epi · GitLab

Nov 21, 2022
- [WebAssembly] Disable register coalescing at -O1 · d9ae0788
  Heejin Ahn authored Nov 15, 2022
  d9ae0788
- [SCEV] Iteratively compute ranges for deeply nested expressions. · 5dad4c67
  Florian Hahn authored Nov 21, 2022
  5dad4c67
- Restore global descriptor demangling after D138095 "[asan] Keep Itanium... · db7c8223
  Fangrui Song authored Nov 21, 2022
  db7c8223
- [WebAssembly] Update relaxed-simd instruction names · ae96b5bd
  Thomas Lively authored Nov 21, 2022
  ae96b5bd
- [PowerPC] Extend GlobalISel implementation to emit and/or/xor. · be4a1dfb
  Kai Nacke authored Sep 16, 2022
  be4a1dfb
- [SCEV] Add range test with phi and division. · 535c2da5
  Florian Hahn authored Nov 21, 2022
  535c2da5
- [PowerPC] Add new load/store with length instructions to Future CPU. · bd680704
  Maryam Moghadas authored Oct 28, 2022
  bd680704
- [Passes][VectorCombine] enable early run generally and try load folds · 163bb6d6
  Sanjay Patel authored Nov 21, 2022
  163bb6d6
- Use poison instead of undef as placeholder for vector construction [NFC] · 1e55d5b1
  Manuel Brito authored Nov 21, 2022
  1e55d5b1
- [SLP]Fix PR59098: check if the vector type is scalarized for · ac93b611
  Alexey Bataev authored Nov 21, 2022
  ac93b611
- [AArch64][SME]: Generate streaming-compatible code for fp_to_int and int_to_fp. · 70180ee0
  Hassnaa Hamdi authored Nov 18, 2022
  70180ee0
- [AArch64][SME]: Add precursory tests for D138281 · bc010cec
  Hassnaa Hamdi authored Nov 18, 2022
  
  bc010cec
- [AArch64][NFC] SME2 Add missing tests for usvdot and sumlall instructions · c0414518
  Caroline Concatto authored Nov 21, 2022
  
  c0414518
- [RISCV] Add isel patterns to select slli+shXadd.uw. · 24810acb
  Craig Topper authored Nov 21, 2022
  24810acb
- [X86] Synchronise scheduler classes of... · 746cf4f1
  Simon Pilgrim authored Nov 21, 2022
  746cf4f1
- [AArch64][SME] Always allocate a lazy-save buffer if a function has ZA state. · 3f9d64a2
  Sander de Smalen authored Nov 21, 2022
  3f9d64a2
- [Assignment Tracking][25/*] Replace sunk address uses in dbg.assign intrinsics · 3115e682
  OCHyams authored Nov 21, 2022
  3115e682
- [X86] Pre-commit tests for pr58685 (negated cases) · 8cce9d7f
  Phoebe Wang authored Nov 21, 2022
  
  8cce9d7f
- [XCOFF] llvm-readobj support display symbol table of loader section of xcoff object file. · a56d0e84
  zhijian authored Nov 21, 2022
  a56d0e84
- [LoopFlatten] Add a test for incorrect IV increment uses. NFC · c7a53421
  David Green authored Nov 21, 2022
  c7a53421
- [NFC][InstCombine] Pre-commit tests for D137934 · 9ab2969e
  Thomas Symalla authored Nov 21, 2022
  9ab2969e
- [DAGCombiner] fold or (and x, y), x --> x · ac1b999e
  chenglin.bi authored Nov 21, 2022
  ac1b999e
- [llvm,polly,clang] Stop setting config.enable_shared in most places · 281a5c7e
  Nico Weber authored Nov 18, 2022
  281a5c7e
- [AArch64][SVE] Precommit tests for VSCALE/SVE CNTx demanded bits · b2505bfb
  Benjamin Maxwell authored Nov 21, 2022
  
  b2505bfb
- Mark test using -debug-only as requiring assertions · 8db98599
  Benjamin Kramer authored Nov 21, 2022
  
  8db98599
- [MachineTraceMetrics] Pick the trace successor for an entry block · fb47bb37
  Anton Sidorenko authored Nov 18, 2022
  fb47bb37
- [MachineTraceMetrics] Precommit test for D138272 · 0c22cdfd
  Anton Sidorenko authored Nov 18, 2022
  
  0c22cdfd
- [Test] Add some test showing limitations of makeIVComparisonInvariant · 41e41cc2
  Max Kazantsev authored Nov 21, 2022
  41e41cc2
- [LoongArch] AsmParser support for the li.[wd] pseudo instructions · f873c50c
  wanglei authored Nov 21, 2022
  f873c50c
- [RISCV] Enable reduction pattern SelectICmp and SelectFCmp. · 846cdf01
  Mel Chen authored Nov 14, 2022
  846cdf01
- [Test] One more test for IndVars, showing imperfect work with context · 5a62e6b4
  Max Kazantsev authored Nov 21, 2022
  
  5a62e6b4
- [LoongArch] Support parsing la* pseudo instructions · a7ec7f6d
  wanglei authored Nov 21, 2022
  a7ec7f6d
- [Test] Add some examples where IndVars fails to turn condition into invariant · c61f37b9
  Max Kazantsev authored Nov 21, 2022
  
  c61f37b9
- [PowerPC] XCOFF exception section support on the integrated assembler path · 22340982
  Paul Scoropan authored Nov 21, 2022
  22340982
- [LoongArch] Make function name in error message consistent with the user input. NFC · f6d411f5
  gonglingqin authored Nov 21, 2022
  
  f6d411f5
- [CSKY] Lower ISD::ConstantPool node to support getting the address of ConstantPool entry · f4d61cdf
  Zi Xuan Wu (Zeson) authored Nov 21, 2022
  f4d61cdf
- [LoongArch] Add intrinsics for ibar, break and syscall · c2ec455f
  gonglingqin authored Nov 21, 2022
  c2ec455f
Nov 20, 2022
- [TableGen] Fix SubRegIndex size computation for concatenated subregs of unknown size · 294fdd99
  Bjorn Pettersson authored Nov 19, 2022
  294fdd99
- [TableGen] Let -register-info-debug dump Offset/Size for each SubRegIndex · a6cb924a
  Bjorn Pettersson authored Nov 19, 2022
  a6cb924a
- [X86] IceLakeServer - PACKS instructions take latency 3cy · 89365b15
  Simon Pilgrim authored Nov 20, 2022
  89365b15