Commits · dad553a5cf9d49493d64a8d55683338336f1a9f9 · Roger Ferrer / llvm-epi · GitLab

Nov 25, 2016
- Revert "AMDGPU: Fix MMO when splitting spill" · dad553a5
  Marek Olsak authored Nov 25, 2016
  dad553a5
- Revert "AMDGPU: Fix adding extra implicit def of register" · 8cbbf653
  Marek Olsak authored Nov 25, 2016
  8cbbf653
- Revert "AMDGPU: Fix not setting kill flag on temp reg when spilling" · 713e6fc5
  Marek Olsak authored Nov 25, 2016
  713e6fc5
- Revert "AMDGPU: Make m0 unallocatable" · a45dae45
  Marek Olsak authored Nov 25, 2016
  a45dae45
- Revert "AMDGPU: Remove m0 spilling code" · ea848df8
  Marek Olsak authored Nov 25, 2016
  ea848df8
- Revert "AMDGPU: Preserve m0 value when spilling" · 18a95bcb
  Marek Olsak authored Nov 25, 2016
  18a95bcb
- [mips] Correct jal expansion for local symbols in .local directives. · c08af6db
  Simon Dardis authored Nov 25, 2016
  c08af6db
- [X86] Invert an 'if' and early out to fix a weird indentation. NFCI · d4091494
  Craig Topper authored Nov 25, 2016
  d4091494
- [X86] Size a SmallVector to the worst case mask size for a 512-bit shuffle. NFCI · a4693618
  Craig Topper authored Nov 25, 2016
  a4693618
Nov 24, 2016
- Fix unused variable warning · f1ee930d
  Simon Pilgrim authored Nov 24, 2016
  f1ee930d
- [X86] Don't round trip a unique_ptr through a raw pointer for assignment. · fc54e35d
  Benjamin Kramer authored Nov 24, 2016
  fc54e35d
- [X86][SSE] Improve UINT_TO_FP v2i32 -> v2f64 · 9c71e072
  Simon Pilgrim authored Nov 24, 2016
  9c71e072
- [X86][AVX512] Add support for v2i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets · 841d7ca4
  Simon Pilgrim authored Nov 24, 2016
  841d7ca4
- [X86][AVX512DQVL] Add awareness of vcvtqq2ps and vcvtuqq2ps implicit zeroing... · 7c26a6f9
  Simon Pilgrim authored Nov 24, 2016
  7c26a6f9
- [X86][AVX512DQVL] Add support for v2i64 -> v2f32 SINT_TO_FP/UINT_TO_FP lowering · ab323ec4
  Simon Pilgrim authored Nov 24, 2016
  ab323ec4
- [x86] Fixing PR28755 by precomputing the address used in CMPXCHG8B · 3a8d108b
  Nikolai Bozhenov authored Nov 24, 2016
  3a8d108b
- [x86] Minor refactoring of X86TargetLowering::EmitInstrWithCustomInserter · bb64aa14
  Nikolai Bozhenov authored Nov 24, 2016
  bb64aa14
- [x86] Rewrite getAddressFromInstr helper function · a2dabed3
  Nikolai Bozhenov authored Nov 24, 2016
  a2dabed3
- [X86] Generalize CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes. NFCI · a3af7967
  Simon Pilgrim authored Nov 24, 2016
  a3af7967
- AMDGPU: Preserve m0 value when spilling · 7b54dd03
  Matt Arsenault authored Nov 24, 2016
  7b54dd03
- TRI: Add hook to pass scavenger during frame elimination · 94b32ffe
  Matt Arsenault authored Nov 24, 2016
  94b32ffe
- AMDGPU: Remove m0 spilling code · 5ee33253
  Matt Arsenault authored Nov 24, 2016
  5ee33253
- AMDGPU: Make m0 unallocatable · 9e5c7b10
  Matt Arsenault authored Nov 24, 2016
  9e5c7b10
Nov 23, 2016
- [X86][SSE] Add awareness of (v)cvtpd2dq and vcvtpd2udq implicit zeroing of... · 3ce6a545
  Simon Pilgrim authored Nov 23, 2016
  3ce6a545
- AMDGPU: Cleanup immediate folding code · a24d84be
  Matt Arsenault authored Nov 23, 2016
  a24d84be
- AMDGPU: Fix debug printing · 391c3ea9
  Matt Arsenault authored Nov 23, 2016
  391c3ea9
- AMDGPU: Fix not setting kill flag on temp reg when spilling · 997a9abf
  Matt Arsenault authored Nov 23, 2016
  997a9abf
- AMDGPU: Fix adding extra implicit def of register · dd0cb2a3
  Matt Arsenault authored Nov 23, 2016
  dd0cb2a3
- AMDGPU: Fix MMO when splitting spill · 2669a76f
  Matt Arsenault authored Nov 23, 2016
  2669a76f
- [X86] Allow folding of stack reloads when loading a subreg of the spilled reg · 47eb85a0
  Michael Kuperstein authored Nov 23, 2016
  47eb85a0
- [PowerPC] Remove InstAlias definitions that cause incorrect assembly · 10fc3cfc
  Nemanja Ivanovic authored Nov 23, 2016
  10fc3cfc
- [X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets · 4e9b9cbe
  Simon Pilgrim authored Nov 23, 2016
  4e9b9cbe
- [CostModel][X86] Add missing AVX512DQ v8i64 fptosi/sitofp costs · 03cd8f88
  Simon Pilgrim authored Nov 23, 2016
  03cd8f88
- [AVX-512] Remove intrinsics for valignd/q and autoupgrade them to native shuffles. · f57e17de
  Craig Topper authored Nov 23, 2016
  f57e17de
- [X86] Simplify lowerVectorShuffleAsBitMask to handle only integer VT's · 14aba43e
  Zvi Rackover authored Nov 23, 2016
  14aba43e
- [xray] Add XRay support for Mach-O in CodeGen · 06995e86
  Kuba Mracek authored Nov 23, 2016
  06995e86
Nov 22, 2016
- TargetSubtargetInfo: Move implementation to lib/CodeGen; NFC · 7f423442
  Matthias Braun authored Nov 22, 2016
  7f423442
- [mips] seb, seh instruction aliases · 6efb8dd2
  Simon Dardis authored Nov 22, 2016
  6efb8dd2
- [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE · b8e30d6d
  Nemanja Ivanovic authored Nov 22, 2016
  b8e30d6d
- [X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles. · 4aa876ca
  Simon Pilgrim authored Nov 22, 2016
  4aa876ca