Commits · db6911a6f9592fa394c0e0a1c0cf268a696e018f · Roger Ferrer / llvm-epi · GitLab

Jun 21, 2018
- AMDGPU: Remove old-style image intrinsics · db6911a6
  Nicolai Haehnle authored Jun 21, 2018
  db6911a6
- InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded · b29ee701
  Nicolai Haehnle authored Jun 21, 2018
  b29ee701
- AMDGPU: Select MIMG instructions manually in SITargetLowering · 7a9c03f4
  Nicolai Haehnle authored Jun 21, 2018
  7a9c03f4
- AMDGPU: Refactor MIMG instruction TableGen using generic tables · 0ab200b6
  Nicolai Haehnle authored Jun 21, 2018
  0ab200b6
- AMDGPU: Use generic tables instead of SearchableTable · e741d7e0
  Nicolai Haehnle authored Jun 21, 2018
  e741d7e0
- AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM) · 2367f035
  Nicolai Haehnle authored Jun 21, 2018
  2367f035
- AMDGPU: Add implicit def of SCC to kill and indirect pseudos · b3a9b685
  Nicolai Haehnle authored Jun 21, 2018
  b3a9b685
- AMDGPU: Turn D16 for MIMG instructions into a regular operand · f2674319
  Nicolai Haehnle authored Jun 21, 2018
  f2674319
- TableGen: Allow foreach in multiclass to depend on template args · 7d69e0f3
  Nicolai Haehnle authored Jun 21, 2018
  7d69e0f3
- [DA] Enable -da-delinearize by default · d143c65d
  David Green authored Jun 21, 2018
  d143c65d
- [X86][AVX] Reduce v4f64/v4i64 shuffle costs (PR37882) · 2a9cde02
  Simon Pilgrim authored Jun 21, 2018
  2a9cde02
- [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property · 42f7bc96
  Mikael Holmen authored Jun 21, 2018
  42f7bc96
- [DAGCombine] Fix alignment for offset loads/stores · a4651885
  David Green authored Jun 21, 2018
  a4651885
- Remove FIXME comment about WIP. · 12e221d9
  Eric Christopher authored Jun 21, 2018
  12e221d9
- Add some explanatory text to the associated symbol support. · 76cfef46
  Eric Christopher authored Jun 21, 2018
  76cfef46
- Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp instructions. · d36aa1f7
  Florian Hahn authored Jun 21, 2018
  d36aa1f7
- [DebugInfo] Keep DBG_VALUE undef in LiveDebugVariables · 57b33f6a
  Mikael Holmen authored Jun 21, 2018
  57b33f6a
- [PM/LoopUnswitch] Add partial non-trivial unswitching for invariant · d1dab0c3
  Chandler Carruth authored Jun 21, 2018
  d1dab0c3
- ProvenanceAnalysis: Store WeakTrackingVH instead of Value* in UnderlyingValue Cache. · 336d75cc
  Michael Zolotukhin authored Jun 21, 2018
  336d75cc
- [X86] Remove masking from 512-bit floating max/min intrinsics. Use select instruction instead. · 296526bf
  Craig Topper authored Jun 21, 2018
  296526bf
- Revert "[SCEV] Improve zext(A /u B) and zext(A % B)" · 433b9761
  Tim Shen authored Jun 21, 2018
  433b9761
- [SCEV] Improve zext(A /u B) and zext(A % B) · 5af61e0a
  Tim Shen authored Jun 21, 2018
  5af61e0a
- [DWARF] Improved error reporting for range lists. · 61d8c8d9
  Wolfgang Pieb authored Jun 20, 2018
  61d8c8d9
- [mips] Add microMIPS specific addressing patterns. · 0f111dd7
  Simon Dardis authored Jun 20, 2018
  0f111dd7
- Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred. · dfd14ade
  Alina Sbirlea authored Jun 20, 2018
  dfd14ade
Jun 20, 2018
- [MemorySSA] Verify Phi incoming blocks are block predecessors. · 201d02c7
  Alina Sbirlea authored Jun 20, 2018
  201d02c7
- [X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel · c2696d57
  Craig Topper authored Jun 20, 2018
  c2696d57
- [SLPVectorizer] Provide InstructionsState down the BoUpSLP vectorization call tree · 3d1c8c97
  Simon Pilgrim authored Jun 20, 2018
  3d1c8c97
- Allow binop C1, (select cc, CF, CT) -> select folding · 20279dc0
  Stanislav Mekhanoshin authored Jun 20, 2018
  20279dc0
- [mips] Correct predicates for loads, bit manipulation instructions and some pseudos · 6021424c
  Simon Dardis authored Jun 20, 2018
  6021424c
- AMDGPU: Fix scalar_to_vector for v4i16/v4f16 · 5a4ec812
  Matt Arsenault authored Jun 20, 2018
  5a4ec812
- AMDGPU: Fix missing C++ mode comment · 3d06668a
  Matt Arsenault authored Jun 20, 2018
  3d06668a
- [IR] add/use isIntDivRem convenience function · 35975884
  Sanjay Patel authored Jun 20, 2018
  35975884
- [PM/LoopUnswitch] Support partial trivial unswitching. · 4da3331d
  Chandler Carruth authored Jun 20, 2018
  4da3331d
- [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w · fafdebcf
  Alex Bradbury authored Jun 20, 2018
  fafdebcf
- [Local] Generalize insertReplacementDbgValues, NFC · 4e93f3dc
  Vedant Kumar authored Jun 20, 2018
  4e93f3dc
- [PredicateInfo] Order instructions in different BBs by DFSNumIn. · 5ac26298
  Florian Hahn authored Jun 20, 2018
  5ac26298
- [DWARF] Don't keep a ref to possibly stack allocated data. · 8e3e374e
  Paul Robinson authored Jun 20, 2018
  8e3e374e
- IRMover: Account for matching types present across modules · 34b91122
  Vlad Tsyrklevich authored Jun 20, 2018
  34b91122
- [Local] Add a utility to insert replacement dbg.values, NFC · 6fa24b0b
  Vedant Kumar authored Jun 20, 2018
  6fa24b0b