Commits · dbaa6a1858a42f72b683f700d3bd7a9632f7a518 · Roger Ferrer / llvm-epi · GitLab

Jan 14, 2021
- Revert "[AArch64] Attempt to sink mul operands" · dbaa6a18
  Martin Storsjö authored Jan 14, 2021
  dbaa6a18
- [TableGen] Enhance !cast<string> to handle bit and bits types. · a022be62
  Paul C. Anagnostopoulos authored Jan 12, 2021
  a022be62
- [InferFunctionAttrs] Improve CHECK variable names (NFC). · c23e34e6
  Florian Hahn authored Jan 14, 2021
  
  c23e34e6
- [X86] Improve sum-of-reductions v4f32 test coverage · 8f1d7f37
  Simon Pilgrim authored Jan 14, 2021
  8f1d7f37
- [SLP] Don't vectorize stores of non-packed types (like i1, i2) · d58512b2
  Bjorn Pettersson authored Dec 28, 2020
  d58512b2
- [AArch64] Adding ACLE intrinsics for the LS64 extension · 2b1e25be
  Lucas Prates authored Dec 10, 2020
  2b1e25be
- [PowerPC] Try to fold sqrt/sdiv test results with the branch. · ff40fb07
  Esme-Yi authored Jan 14, 2021
  ff40fb07
- [RISCV] Custom lower ISD::VSCALE. · dfc1901d
  Craig Topper authored Jan 13, 2021
  dfc1901d
- [SystemZ] Clear Available set in SystemZPostRASchedStrategy::initialize(). · ddd03842
  Jonas Paulsson authored Jan 11, 2021
  ddd03842
Jan 13, 2021
- [SPARC] Fix fp128 load/stores · 7ec8f436
  Craig Topper authored Jan 13, 2021
  7ec8f436
- [NewPM] Only non-trivially loop unswitch at -O3 and for non-optsize functions · 39e6d242
  Arthur Eubanks authored Jan 12, 2021
  39e6d242
- Revert "[AsmParser] make .ascii support spaces as separators" · 82c4153e
  Jian Cai authored Jan 13, 2021
  82c4153e
- [DSE] Add tests with stores of existing values. · 6077d553
  Florian Hahn authored Jan 13, 2021
  6077d553
- [FuncAttrs] Add additional willreturn tests (NFC) · f711cb9a
  Nikita Popov authored Jan 13, 2021
  
  f711cb9a
- [LTO] Add test for freestanding LTO option. · 01c31358
  Florian Hahn authored Jan 13, 2021
  01c31358
- [CSSPGO][llvm-profgen] Virtual unwinding with pseudo probe · c681400b
  wlei authored Nov 25, 2020
  c681400b
- [CSSPGO][llvm-profgen] Pseudo probe decoding and disassembling · b3154d11
  wlei authored Nov 23, 2020
  b3154d11
- [ARM] Add a pass that re-arranges blocks when there is a backwards WLS branch · 60fda8eb
  Sam Tebbs authored Nov 26, 2020
  60fda8eb
- [X86][AVX] Add test for another 'reverse HADD' pattern mentioned in PR41813 · efb6e45d
  Simon Pilgrim authored Jan 13, 2021
  
  efb6e45d
- [X86][SSE] canonicalizeShuffleMaskWithHorizOp - simplify... · cbbfc825
  Simon Pilgrim authored Jan 13, 2021
  cbbfc825
- [dsymutil] Warn on timestmap mismatch between object file and debug map · 48d2068f
  Jonas Devlieghere authored Jan 13, 2021
  48d2068f
- [IROutliner] Adapting to hoisted bitcasts in CodeExtractor · 05b1a15f
  Andrew Litteken authored Jan 07, 2021
  05b1a15f
- [InstCombine] Fold select -> and/or using impliesPoison · 17863614
  Nikita Popov authored Jan 12, 2021
  17863614
- [SLP] add reduction test for FMF; NFC · e433ca28
  Sanjay Patel authored Jan 13, 2021
  
  e433ca28
- [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type · 4e8e8889
  Muhammad Asif Manzoor authored Jan 13, 2021
  4e8e8889
- [NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32. · 350c0552
  Hsiangkai Wang authored Jan 13, 2021
  350c0552
- GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper · d55d592a
  Matt Arsenault authored Aug 19, 2020
  d55d592a
- [AArch64] Attempt to sink mul operands · dda60035
  Nicholas Guy authored Dec 02, 2020
  dda60035
- [X86] Add tests for rv_marker lowering. · b7b1e8c3
  Florian Hahn authored Jan 13, 2021
  b7b1e8c3
- [Tests] Added test for memcpy loop idiom recognization · d307d892
  Dávid Bolvanský authored Jan 13, 2021
  
  d307d892
- [SVE][CodeGen] CTLZ, CTTZ & CTPOP operations (predicates) · 2170e0ee
  Kerry McLaughlin authored Jan 13, 2021
  2170e0ee
- Revert "[dsymutil] Warn on timestmap mismatch between object file and debug map" · c6e341c8
  David Zarzycki authored Jan 13, 2021
  c6e341c8
- [LTO] Add test to ensure objc-arc-contract is executed. · ada96fa6
  Florian Hahn authored Jan 13, 2021
  ada96fa6
- [SVE] Add ISel pattern for addvl · ad85e396
  Cullen Rhodes authored Jan 12, 2021
  ad85e396
- [X86][AVX] combineVectorSignBitsTruncation - limit AVX512 truncations to 128-bits (PR48727) · 0f59d099
  Simon Pilgrim authored Jan 13, 2021
  0f59d099
- [AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics · 3122c66a
  Joe Ellis authored Jan 11, 2021
  3122c66a
- [obj2yaml,yaml2obj] - Refine how we set/dump the sh_entsize field. · 6d3098e7
  Georgii Rymar authored Dec 28, 2020
  6d3098e7
- [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors · c29ca855
  David Green authored Jan 13, 2021
  c29ca855
- [llvm-readelf/obj] - Add support of multiple SHT_SYMTAB_SHNDX sections. · 141906fa
  Georgii Rymar authored Dec 08, 2020
  141906fa
- [ARM] Additional tests for different interleaving patterns. NFC · 3aeb30d1
  David Green authored Jan 13, 2021
  
  3aeb30d1