Commits · dbbd6276f20aa8bcf472f12a16a5a895ff797313 · Roger Ferrer / llvm-epi · GitLab

Jun 13, 2023
- [AArch64] Try to combine MULL with uzp1. · 16daaf08
  Jingu Kang authored May 31, 2023
  16daaf08
- [X86] X86FixupVectorConstantsPass - attempt to replace full width fp vector... · 834cc88c
  Simon Pilgrim authored Jun 13, 2023
  834cc88c
- [AArch64][SVE] Extra patterns for predicated and/or/xor · 16c4de1f
  David Green authored Jun 13, 2023
  16c4de1f
- MachineConstantPool::getConstantPoolIndex - don't reuse mismatched constants... · e61bb1e5
  Simon Pilgrim authored Jun 13, 2023
  e61bb1e5
- [GlobalIsel][X86] Regenerate legalize-phi.mir · 35def303
  Simon Pilgrim authored Jun 12, 2023
  
  35def303
- [DAGCombine] Make sure combined nodes are added back to the worklist in topological order. · a70d5e25
  Amaury Séchet authored Jun 07, 2023
  a70d5e25
- AMDGPU: Correct constants used in fast math log expansion · d0923a77
  Matt Arsenault authored Jun 12, 2023
  d0923a77
- AMDGPU: Modernize log codegen tests · 1f615b50
  Matt Arsenault authored Jun 10, 2023
  
  1f615b50
- AMDGPU: Add llvm.amdgcn.log intrinsic · eccc89b2
  Matt Arsenault authored Jun 11, 2023
  eccc89b2
- LowerMemIntrinsics: Handle inserting addrspacecast for memmove lowering · ee19fabc
  Matt Arsenault authored Jun 10, 2023
  ee19fabc
- [RISC-V] Zvk update to 0.9.7, Zvknc/Zvksc · c5a88fe3
  Eric Gouriou authored Jun 12, 2023
  c5a88fe3
Jun 12, 2023
- [RISCV] Use TU vmv.v.v instead of vslideup.vi N,M,0 for insert vector_shuffles · a8499407
  Luke Lau authored Jun 12, 2023
  a8499407
- [DAGCombine] Use `IsKnownNeverZero` to see if we need zero-check in is_pow2 setcc patern · 5c8188c7
  Noah Goldstein authored Jun 12, 2023
  5c8188c7
- [X86] Add tests for optimizing out zero-check in is_pow2 setcc pattern; NFC · 4e2b532c
  Noah Goldstein authored Jun 11, 2023
  4e2b532c
- [RISCV] Fold binary op into select if profitable. · d0189584
  Mikhail Gudim authored Jun 12, 2023
  d0189584
- [RISCV] Use tail undisturbed vmv.v.v instead of vadd.vi with 0 for vp.merge with all ones mask. · c5fdab30
  Craig Topper authored Jun 12, 2023
  c5fdab30
- [RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion · 17e2d07a
  Craig Topper authored Jun 12, 2023
  17e2d07a
- [RISCV] Don't use (ADD (SLLI C, 32), C) to materialize constants when optimizing for size. · b418482f
  Craig Topper authored Jun 12, 2023
  b418482f
- [SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM · b2195bc7
  Anna Thomas authored Jun 12, 2023
  b2195bc7
- [AMDGPU] Fix resource-usage-pal.ll · 9eea63bc
  Kazu Hirata authored Jun 12, 2023
  
  9eea63bc
- [AMDGPU] Do not assume stack size for PAL code object indirect calls · 3604fdf1
  Baptiste authored Jun 12, 2023
  3604fdf1
- [AMDGPU][GFX11] Add test coverage for cases involving conversions from and to fp16 values. · d09fa8ff
  Ivan Kosarev authored Jun 12, 2023
  d09fa8ff
- [MISched] Require asserts and AArch64 registered target for test. · 45902a25
  Francesco Petrogalli authored Jun 12, 2023
  45902a25
- [GlobalIsel][X86] Rename x86_64-select-fcmp.mir to select-fcmp.mir and add 32-bit test coverage · 3d34f7be
  Simon Pilgrim authored Jun 12, 2023
  3d34f7be
- [GlobalIsel][X86] Move G_FCMP getActionDefinitionsBuilder out of... · 22c17c6a
  Simon Pilgrim authored Jun 12, 2023
  22c17c6a
- [GlobalIsel][X86] Regenerate legalize-fcmp.mir · 6a12ab87
  Simon Pilgrim authored Jun 12, 2023
  
  6a12ab87
- [GlobalIsel][X86] Rename x86_64-legalize-fcmp to legalize-fcmp · 1a576aa0
  Simon Pilgrim authored Jun 12, 2023
  1a576aa0
- [LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops · 2a1716de
  Luke Lau authored Jun 06, 2023
  2a1716de
- [MISched] Use StartAtCycle in trace dumps. · 15a16ef8
  Francesco Petrogalli authored Jun 12, 2023
  15a16ef8
- [XRay] Rename XRayOmitFunctionIndex to XRayFunctionIndex · 849f1dd1
  Fangrui Song authored Jun 11, 2023
  849f1dd1
Jun 11, 2023
- [AArch64][ARM][X86] Split XRay tests for Linux/macOS · c72dea88
  Oleksii Lozovskyi authored Jun 11, 2023
  c72dea88
- [GlobalIsel][X86] Ensure bit count legalizer patterns keep matching result + input scalar types · 26706807
  Simon Pilgrim authored Jun 11, 2023
  
  26706807
- [AVR] Optimize 8-bit rotation when rotation bits == 3 · 71d90f31
  Ben Shi authored Jun 11, 2023
  71d90f31
- [AVR] Optimize 8-bit rotation when rotation bits >= 4 · e21df829
  Ben Shi authored Jun 11, 2023
  e21df829
Jun 10, 2023
- [X86] Make constant `mul` -> `shl` + `add`/`sub` work for vector types · b6808ba2
  Noah Goldstein authored Jun 10, 2023
  b6808ba2
- LowerMemIntrinsics: Skip memmove with different address spaces · 6d2e5c34
  Matt Arsenault authored Jun 10, 2023
  6d2e5c34
- [AVR] Fix incorrect expansion of pseudo instruction ROLBRd · f3837e72
  Ben Shi authored Jun 07, 2023
  f3837e72
- [AVR] Enable sub register liveness · cef723a0
  Ben Shi authored Jun 10, 2023
  cef723a0
- [AVR][NFC] Improve CodeGen tests · 3b8c12c1
  Ben Shi authored Jun 10, 2023
  3b8c12c1
- AMDGPU: Implement known bits functions for min3/max3/med3 · abff7668
  Matt Arsenault authored Jan 27, 2016
  
  abff7668