Commits · dd763ac79196b3d3bc0370b9dbd35e0c083e52a4 · Roger Ferrer / llvm-epi · GitLab

Jun 09, 2021
- [SDAG] fix miscompile from merging stores of different sizes · dd763ac7
  Sanjay Patel authored Jun 09, 2021
  dd763ac7
- [ARM] Fix Machine Outliner LDRD/STRD handling in Thumb mode. · 6c78dbd4
  Yvan Roux authored Jun 09, 2021
  6c78dbd4
- [x86] add tests for store merging miscompile (PR50623); NFC · 2ef81cb2
  Sanjay Patel authored Jun 09, 2021
  
  2ef81cb2
- [X86][SLM] Adjust XMM non-PMULLD throughput costs to half rate. · 630820ba
  Simon Pilgrim authored Jun 09, 2021
  630820ba
- [X86][SSE] Regenerate slow-pmulld.ll test checks · 8ffeb5c4
  Simon Pilgrim authored Jun 09, 2021
  
  8ffeb5c4
- [AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier · d96ea466
  Meera Nakrani authored Jun 02, 2021
  d96ea466
- [ValueTypes][RISCV] Cap RVV fixed-length vectors by size · 502edebd
  Fraser Cormack authored Jun 07, 2021
  502edebd
- [RISCV] Support CONCAT_VECTORS on scalable masks · e8f1f891
  Fraser Cormack authored Jun 08, 2021
  e8f1f891
- [PowerPC] Make sure the first probe is full size or is the last probe when stack is realigned · bf58600b
  Kai Luo authored Jun 09, 2021
  bf58600b
- [RISCV][NFC] Add a single space after comma for VType · 242ddd50
  Jim Lin authored Jun 08, 2021
  242ddd50
- Reland "[AMDGPU] Add gfx1013 target" · 294efbbd
  Brendon Cahoon authored Jun 08, 2021
  294efbbd
Jun 08, 2021
- [SystemZ] Return true from convertSetCCLogicToBitwiseLogic for scalar integer. · 8b32e25b
  Jonas Paulsson authored Jun 01, 2021
  8b32e25b
- [SystemZ] Return true from isMaskAndCmp0FoldingBeneficial(). · d5e4f28c
  Jonas Paulsson authored May 29, 2021
  d5e4f28c
- Revert "[AMDGPU] Add gfx1013 target" · 211e584f
  Brendon Cahoon authored Jun 08, 2021
  211e584f
- Revert "[DSE] Remove stores in the same loop iteration" · 297088d1
  David Green authored Jun 08, 2021
  297088d1
- [ARM] Generate VDUP(Const) from constant buildvectors · d7853bae
  David Green authored Jun 08, 2021
  d7853bae
- [amdgpu] Add `-enable-ocl-mangling-mismatch-workaround`. · 27332968
  Michael Liao authored Jun 08, 2021
  27332968
- GlobalISel: Avoid use of G_INSERT in insertParts · 31a9659d
  Matt Arsenault authored Jun 07, 2021
  31a9659d
- [ARM] A couple of extra VMOVimm tests, useful for showing BE codegen. NFC · f44770c3
  David Green authored Jun 08, 2021
  
  f44770c3
- [RISCV] Remove dead code from fixed-vectors-abs.ll test cases. NFC · c09b3755
  Craig Topper authored Jun 08, 2021
  c09b3755
- reland [IR] make -stack-alignment= into a module attr · 3787ee45
  Nick Desaulniers authored Jun 08, 2021
  3787ee45
- [GlobalISel] Handle non-multiples of the base type in narrowScalarAddSub · 4271e1d2
  Justin Bogner authored Mar 02, 2021
  4271e1d2
- [GlobalISel] Handle non-multiples of the base type in narrowScalarInsert · 2a7e7597
  Justin Bogner authored Mar 02, 2021
  2a7e7597
- [AMDGPU] Add gfx1013 target · ea10a869
  Brendon Cahoon authored Jun 01, 2021
  ea10a869
- Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. · 8b4c80d3
  Craig Topper authored Jun 08, 2021
  8b4c80d3
- [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions. · c57bce9c
  Craig Topper authored Jun 08, 2021
  c57bce9c
- Revert "[IR] make -stack-alignment= into a module attr" · a596b54d
  Nick Desaulniers authored Jun 08, 2021
  a596b54d
- [IR] make -stack-alignment= into a module attr · 433c8d95
  Nick Desaulniers authored Jun 08, 2021
  433c8d95
- [DAG] foldShuffleOfConcatUndefs - ensure shuffles of upper (undef) subvector... · 61a2d6bf
  Simon Pilgrim authored Jun 08, 2021
  61a2d6bf
- [RISCV] Add a test case showing inefficient vector codegen · ccd1e087
  Fraser Cormack authored Jun 08, 2021
  
  ccd1e087
- [DAG] Allow isNullOrNullSplat to see truncated zeroes · b889c6ee
  David Green authored Jun 08, 2021
  b889c6ee
- [RISCV] Use 0 for Log2SEW for vle1/vse1 intrinsics to enable vsetvli optimization. · 7c4e9a68
  Craig Topper authored Jun 07, 2021
  7c4e9a68
- [RISCV] Masked compares should use a tail agnostic policy. · ae3ab4f0
  Craig Topper authored Jun 07, 2021
  ae3ab4f0
- [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions · f8816c74
  Carl Ritson authored Jun 08, 2021
  f8816c74
- [RISCV] Optimize bitwise and with constant for the Zbs extension · c705b7b0
  Ben Shi authored Jun 08, 2021
  c705b7b0
- Revert "[TargetLowering] Only inspect attributes in the arguments for ArgListEntry" · 47211fa8
  Arthur Eubanks authored Jun 07, 2021
  47211fa8
- [AMDGPU] Handle constant LDS uses from different kernels · 05289dfb
  Stanislav Mekhanoshin authored Jun 07, 2021
  05289dfb
- [AMDGPU] Introduce command line switch to control super aligning of LDS. · 713ca2f3
  hsmahesha authored Jun 08, 2021
  713ca2f3
Jun 07, 2021
- [X32] Add Triple::isX32(), use it. · 75521bd9
  Harald van Dijk authored Jun 07, 2021
  75521bd9
- AMDGPU: Move codegen test out of MIR test directory · ccf28ea8
  Matt Arsenault authored Jun 05, 2021
  ccf28ea8