Commits · dde2a7fb6da46da2b2f765fa569d8fddb4270eb6 · Roger Ferrer / llvm-epi · GitLab

Jul 13, 2022
- [RISCV] Exploit fact that vscale is always power of two to replace urem sequence · dde2a7fb
  Philip Reames authored Jul 12, 2022
  dde2a7fb
- [RISCV][test] Add test of binop followed by extractelement. · 9049c46b
  Jianjian GUAN authored Jul 12, 2022
  9049c46b
- {RISCV] Test coverage for improved lowering assuming vscale is pow-of-two · 1ce3f945
  Philip Reames authored Jul 12, 2022
  
  1ce3f945
Jul 12, 2022
- [TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types. · 8eaf00e0
  Craig Topper authored Jul 09, 2022
  8eaf00e0
- [RISCV] Pre-commit test for PR56457. NFC · 866be0aa
  Craig Topper authored Jul 09, 2022
  
  866be0aa
Jul 11, 2022
- [RISCV] Pre-commit tests for D121833. NFC · ca13555e
  Craig Topper authored Jul 11, 2022
  
  ca13555e
- [RISCV] Optimize 2x SELECT for floating-point types · 3f68f0f8
  LiaoChunyu authored Jul 09, 2022
  3f68f0f8
Jul 10, 2022
- [RISCV] Teach shouldConvertConstantLoadToIntImm that constant materialization... · 35ec8a42
  Craig Topper authored Jul 10, 2022
  35ec8a42
- [RISCV] Add test cases for inline memcpy expansion · 60450f91
  Craig Topper authored Jul 10, 2022
  60450f91
- [RISCV] Modify the custom isel for (add X, imm) used by load/stores. · 5f7641a3
  Craig Topper authored Jul 09, 2022
  5f7641a3
Jul 08, 2022
- [RISCV] Mark fminnum_vl and fmaxnum_vl as commutable. · 92f1794d
  Craig Topper authored Jul 08, 2022
  
  92f1794d
- [RISCV] Add commuted fixed vector vfmax.vf and vfmin.vf tests. NFC · 069ba966
  Craig Topper authored Jul 08, 2022
  069ba966
- [RISCV] Mark vsadd(u)_vl as commutable · 264018d7
  Philip Reames authored Jul 08, 2022
  264018d7
- [RISCV] Mark (s/u)min_vl and (s/u)max_vl as commutable. · a246eb68
  Craig Topper authored Jul 08, 2022
  
  a246eb68
- [RISCV] Add fixed vector vmin(u).vx and vmax(u).vx tests. NFC · cd783bf9
  Craig Topper authored Jul 08, 2022
  
  cd783bf9
- [SDAG] try to replace subtract-from-constant with xor · 8b756713
  Sanjay Patel authored Jul 08, 2022
  8b756713
- [RISCV] Fix wrong register rename for store value during make-compressible optimization · 5c45ae41
  Kito Cheng authored Jul 08, 2022
  5c45ae41
- [RISCV] Precommit testcase to show wrong result of make-compressible optimization · 7b9a3b9d
  Kito Cheng authored Jul 08, 2022
  7b9a3b9d
- [RISCV] Change VECTOR_SPLICE mask operation from expand to promote · 9cfb28d6
  Lian Wang authored Jun 29, 2022
  9cfb28d6
- [RISCV] Recommit test for D128717 · 99da3115
  Lian Wang authored Jul 08, 2022
  99da3115
- Revert "[RISCV] Precommit test for D128717" · ab9e8a3a
  Lian Wang authored Jul 08, 2022
  ab9e8a3a
- [RISCV] Precommit test for D128717 · b3b37f3e
  Lian Wang authored Jun 29, 2022
  b3b37f3e
- Revert "[RISCV] Optimize 2x SELECT for floating-point types" · bf1758c3
  Diego Caballero authored Jul 07, 2022
  bf1758c3
Jul 07, 2022
- [RISCV] Adjust fixed vector coverage for get.active.lane.mask · 439783da
  Philip Reames authored Jul 07, 2022
  439783da
- [RISCV] Test coverage for missing commute of vsadd(u) · fa3783c9
  Philip Reames authored Jul 07, 2022
  fa3783c9
Jul 06, 2022
- [RISCV] Add codegen coverage for get.active.lane.mask · 6f4773f0
  Philip Reames authored Jul 06, 2022
  
  6f4773f0
- [RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1) · 088bb8a3
  Craig Topper authored Jul 05, 2022
  088bb8a3
Jul 05, 2022
- [RISCV] Add more SHXADD tests. NFC · ac3e26bc
  Craig Topper authored Jul 05, 2022
  
  ac3e26bc
Jul 04, 2022
- [RISCV] Add ADDI instr for computing FrameIndex address · c06d0b4d
  luxufan authored Jun 19, 2022
  c06d0b4d
- [RISCV] Add more SHXADD patterns. · d36e09cf
  Craig Topper authored Jul 03, 2022
  d36e09cf
Jul 03, 2022
- [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset · 0f45eaf0
  luxufan authored Jun 18, 2022
  0f45eaf0
- [RISCV] Add more SHXADD isel patterns. · 7e4ab9d5
  Craig Topper authored Jul 02, 2022
  7e4ab9d5
Jul 02, 2022
- [RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C). · b2e9684f
  Craig Topper authored Jul 02, 2022
  b2e9684f
- [RISCV] isel (add (and X, 0xFFFFFFFE), Y) as (SH1ADD (SRLIW X, 1), Y). · 9ac548e1
  Craig Topper authored Jul 01, 2022
  9ac548e1
- [RISCV] Restore "Enable shrink wrap by default" · 5744b9cb
  Yeting Kuo authored Jul 01, 2022
  5744b9cb
Jun 30, 2022
- [RISCV] Make custom isel for (add X, imm) used by load/stores more selective. · 354e0455
  Craig Topper authored Jun 30, 2022
  354e0455
- [RISCV] Fold (sra (add (shl X, 32), C1), 32 - C) -> (shl (sext_inreg (add X, C1), C) · 51d67294
  Craig Topper authored Jun 30, 2022
  51d67294
- [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C). · 9ace5af0
  Craig Topper authored Jun 30, 2022
  9ace5af0
- [RISCV] Pre-commit tests for D128869. NFC · 781e3d7a
  Craig Topper authored Jun 29, 2022
  
  781e3d7a
- [RISCV] Add a test covering a (reverted) codegen issue · d5213c83
  Fraser Cormack authored Jun 30, 2022
  d5213c83