Commits · df4878d28d38b2bf2eb8d50d9cdef93ab79a38d5 · Roger Ferrer / llvm-epi · GitLab

Aug 15, 2022
- [AArch64] Tests for non-temporal loads. · df4878d2
  Zain Jaffal authored Aug 15, 2022
  df4878d2
- [X86][RISCV] Pre-commit tests for D130862. NFC · b8c5420d
  Craig Topper authored Aug 14, 2022
  b8c5420d
Aug 14, 2022
- [Hexagon] Distribute disjoint intervals at the end of expand-condsets · 40ba7867
  Krzysztof Parzyszek authored Aug 14, 2022
  40ba7867
- [X86] combineVectorShiftImm - fold (shl (add X, X), C) -> (shl X, (C + 1)) · 8b47e29f
  Simon Pilgrim authored Aug 14, 2022
  8b47e29f
- [X86] Add test coverage for lshr/ashr with freeze · b3452c95
  Simon Pilgrim authored Aug 14, 2022
  
  b3452c95
- [DAG] canCreateUndefOrPoison - add freeze(shl(x,y)) -> shl(freeze(x),y) support · e2d13fd0
  Simon Pilgrim authored Aug 14, 2022
  e2d13fd0
- [X86] Add test coverage for shl nsw with freeze · 3dba35b6
  Simon Pilgrim authored Aug 14, 2022
  
  3dba35b6
- [X86] freeze-binary.ll - tweak freeze_mul_nsw test to avoid mul by pow-2 · ed0074bd
  Simon Pilgrim authored Aug 14, 2022
  ed0074bd
- [X86] Add test coverage for shl with freeze · 59d0e0d9
  Simon Pilgrim authored Aug 14, 2022
  
  59d0e0d9
- [DAG] canCreateUndefOrPoison - add freeze(and/or/xor(x,y)) -> and/or/xor(freeze(x),y) support · a621d38b
  Simon Pilgrim authored Aug 14, 2022
  a621d38b
- [X86] Add test coverage for and/or/xor with freeze · 0f7ecba9
  Simon Pilgrim authored Aug 14, 2022
  
  0f7ecba9
- [X86][FP16] Promote FP16->[U]INT to FP16->FP32->[U]INT · 8b69549d
  Phoebe Wang authored Aug 14, 2022
  8b69549d
Aug 13, 2022
- [AArch64] Fix signed integer overflow in CSINC case · f1596952
  Vitaly Buka authored Aug 12, 2022
  f1596952
- [DAG] canCreateUndefOrPoison - add freeze(add/sub/mul(x,y)) -> add/sub/mul(freeze(x),y,z) support · 60534b88
  Simon Pilgrim authored Aug 13, 2022
  60534b88
- [X86] Add test coverage for add/sub/mul with freeze · 99885368
  Simon Pilgrim authored Aug 13, 2022
  
  99885368
- Revert "[AArch64][GlobalISel] Recognise some CCMPri" · c2af37dc
  Florian Hahn authored Aug 13, 2022
  c2af37dc
- [RISCV] Fold (sub constant, (setcc x, y, eq/neq)) -> (add constant - 1, (setcc x, y, neq/eq)) · 99ef0dde
  LiaoChunyu authored Aug 13, 2022
  99ef0dde
- (Reland) [fastalloc] Support allocating specific register class in fastalloc · 30f9e6eb
  Luo, Yuanke authored Jun 23, 2022
  30f9e6eb
Aug 12, 2022
- X86: Don't fold TEST into ADD ...@GOTTPOFF/GOTNTPOFF/INDNTPOFF · 4d7f9b74
  James Y Knight authored Aug 11, 2022
  4d7f9b74
- [SPIRV] support capabilities and extensions · df871307
  Ilia Diachkov authored Aug 11, 2022
  df871307
- [DAGCombine] Hoist shifts out of a logic operations tree. · 1626ee6a
  Filipp Zhinkin authored Aug 04, 2022
  1626ee6a
- [NFC] Split test to reduce time to run. · 5eeef48e
  Daniil Fukalov authored Aug 01, 2022
  5eeef48e
- [PowerPC] Fix test case changed by "Add XXEVAL TD pattern" [NFC] · 13c1e7a8
  Ting Wang authored Aug 12, 2022
  
  13c1e7a8
- [LoongArch] Add codegen support for ISD::CTPOP, ISD::CTTZ and ISD::CTLZ · 9e09c318
  gonglingqin authored Aug 12, 2022
  9e09c318
- [PowerPC] Add XXEVAL TD pattern · 12e1936f
  Ting Wang authored Aug 12, 2022
  12e1936f
- [PowerPC] omit location attribute for TLS variable on AIX · 8d19cfb7
  Chen Zheng authored Jul 21, 2022
  8d19cfb7
- [RISCV] Use SLTIU X, -1 for (setne X, -1). · e493944f
  Craig Topper authored Aug 11, 2022
  e493944f
Aug 11, 2022
- [RISCV] Add more ineg+setcc isel patterns to avoid creating neg+xori+slti(u). · 2c79801a
  Craig Topper authored Aug 11, 2022
  2c79801a
- [X86] lowerShuffleWithVPMOV - support direct lowering to VPMOV on VLX targets · 6ba5fc2d
  Simon Pilgrim authored Aug 11, 2022
  6ba5fc2d
- [X86] vector-rotate-128/265.ll - add VLX + NOVLX check prefixes to reduce CHECK duplication · d4a4864c
  Simon Pilgrim authored Aug 11, 2022
  
  d4a4864c
- [AMDGPU] Autogenerate spill-vector-superclass. NFC · b92161f9
  Joe Nash authored Aug 11, 2022
  b92161f9
- [AArch64] Add bf16 select handling · a9e9dd9a
  David Green authored Aug 11, 2022
  a9e9dd9a
- AMDGPU: mbcnt allow for non-zero src1 for known-bits · 1d1cc055
  David Stuttard authored Aug 09, 2022
  1d1cc055
- [RISCV] Peephole optimization to fold merge.vvm and unmasked intrinsics. · 87569408
  Yeting Kuo authored Jul 16, 2022
  87569408
- [COFF] Emit embedded -exclude-symbols: directives for hidden visibility for MinGW · c5b3de67
  Martin Storsjö authored Jul 19, 2022
  c5b3de67
- [TypePromotion] Search from ZExt + PHI · 16406791
  Andre Vieira authored Aug 11, 2022
  16406791
- [RISCV][test] Precommitted test for optimization for vmerge and unmasked intrinsics. · 7050f210
  Yeting Kuo authored Jul 29, 2022
  7050f210
- [XCOFF] ignore the cold attribute. · 7a70e6e2
  esmeyi authored Aug 11, 2022
  7a70e6e2
- [CodeGen] Generate efficient assembly for freeze(poison) version of `mm*_cast*` intel intrinsics · 02e56e25
  aqjune authored Jun 27, 2022
  02e56e25
- [LoongArch] Override TargetLowering::isOffsetFoldingLegal() · c437412f
  wanglei authored Aug 11, 2022
  c437412f