Commits · dfec0b3053b9d433fa3770ff31bc540406db4ba8 · Roger Ferrer / llvm-epi · GitLab

Feb 15, 2022
- [X86] LowerVSETCC - always split 512-bit vectors before lowering to PCMPEQ/GT (PR53842) · 2808743c
  Simon Pilgrim authored Feb 15, 2022
  2808743c
- [X86][Win64] Avoid statepoints in trailing call position · 78c27a3c
  Markus Böck authored Feb 13, 2022
  78c27a3c
Feb 13, 2022
- [X86] combineArithReduction - pull out (near) duplicate v4i8/v8i8 widening code. NFC. · 890beda4
  Simon Pilgrim authored Feb 13, 2022
  
  890beda4
- [x86] try harder to scalarize a vector load with extracted integer op uses · c486b82c
  Sanjay Patel authored Feb 13, 2022
  c486b82c
- [X86][MS] Fix the wrong alignment of vector variable arguments on Win32 · 2aa732a9
  Phoebe Wang authored Feb 13, 2022
  2aa732a9
Feb 12, 2022
- [X86] LowerFunnelShift - enable v16i16 support · 9c55b0e1
  Simon Pilgrim authored Feb 12, 2022
  
  9c55b0e1
- [X86] combineAndnp - if an input has a zero (after inversion for Op0) in a... · a4ed0c2f
  Simon Pilgrim authored Feb 12, 2022
  a4ed0c2f
- [X86] getTargetVShiftNode - Fix Wparentheses gcc warning. · 1f433673
  Simon Pilgrim authored Feb 12, 2022
  
  1f433673
- [X86] combineAndnp - pull out repeated operands. NFC. · 6320c3e7
  Simon Pilgrim authored Feb 12, 2022
  
  6320c3e7
- [X86] combineAnd - add SimplifyMultipleUseDemandedBits handling to masked vector element analysis · dcf46573
  Simon Pilgrim authored Feb 12, 2022
  dcf46573
- [X86] Improve uniform funnelshift/rotation amount handling · 1e1b6013
  Simon Pilgrim authored Feb 12, 2022
  1e1b6013
- [X86] Enable vector splitting of ISD::AVGCEILU nodes on AVX1 and non-BWI targets · 37cf7275
  Simon Pilgrim authored Feb 12, 2022
  
  37cf7275
Feb 11, 2022
- [X86] Replace X86ISD::AVG with generic ISD::AVGCEILU · f810b40c
  David Green authored Feb 11, 2022
  f810b40c
- [X86] combineVSelectToBLENDV - handle vselect(vXi1,A,B) -> blendv(sext(vXi1),A,B) · 20af71f8
  Simon Pilgrim authored Feb 11, 2022
  20af71f8
- [X86] Move combineToExtendBoolVectorInReg before the select combines. NFC. · 48e1434a
  Simon Pilgrim authored Feb 11, 2022
  48e1434a
- [X86] combineToExtendBoolVectorInReg - use explicit arguments. NFC. · 827d0c51
  Simon Pilgrim authored Feb 11, 2022
  827d0c51
- [X86] Zero out the 32-bit GPRs explicitly · 74aa44a8
  Bill Wendling authored Feb 10, 2022
  74aa44a8
- Reland "[clang-cl] Support the /JMC flag" · f9270214
  Yuanfang Chen authored Feb 10, 2022
  f9270214
Feb 10, 2022
- Revert "[clang-cl] Support the /JMC flag" · b380a31d
  Yuanfang Chen authored Feb 10, 2022
  b380a31d
- [TTI][X86] Pull out repeated getSizeInBits() calls. NFC. · 8c82d42e
  Simon Pilgrim authored Feb 10, 2022
  
  8c82d42e
- [clang-cl] Support the /JMC flag · bd3a1de6
  Yuanfang Chen authored Feb 10, 2022
  bd3a1de6
- [X86] getFMA3OpcodeToCommuteOperands - use unreachable to detect fma3 format mismatch · e95fc20f
  Simon Pilgrim authored Feb 10, 2022
  e95fc20f
- [DebugInfo][InstrRef] Avoid duplicate instruction numbers in x86-lea-fixup · 662799c8
  Jeremy Morse authored Feb 10, 2022
  662799c8
- [X86] Only force FP usage in the presence of pushf/popf on Win64 · f3481f43
  Reid Kleckner authored Feb 09, 2022
  f3481f43
Feb 09, 2022
- [X86] TCRETURNmi fix for 32bit platform · 2fe31516
  Tong Zhang authored Feb 09, 2022
  2fe31516
- Revert "X86: gate all vmovsh instructions on FP16 support." · 8366e182
  Tim Northover authored Feb 09, 2022
  8366e182
- X86: gate all vmovsh instructions on FP16 support. · 3fc40b6e
  Tim Northover authored Feb 07, 2022
  3fc40b6e
- Cleanup LLVMMC headers · ef736a1c
  serge-sans-paille authored Feb 08, 2022
  ef736a1c
- [X86] Specify Undef for the registers we xor · d295a53a
  Bill Wendling authored Feb 09, 2022
  d295a53a
- [X86] Implement -fzero-call-used-regs option · deaf22bc
  Bill Wendling authored Feb 08, 2022
  deaf22bc
Feb 08, 2022
- [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs · 56d6ccd4
  Craig Topper authored Feb 08, 2022
  56d6ccd4
- [X86] selectLEAAddr - relax heuristic to only require one operand to be a... · 0b00cd19
  Simon Pilgrim authored Feb 08, 2022
  0b00cd19
- [SDAG] move x86 select-with-identity-constant fold behind a target hook; NFC · a68e0980
  Sanjay Patel authored Feb 08, 2022
  a68e0980
- [ADT] Add APInt/MathExtras isShiftedMask variant returning mask offset/length · fd2bb51f
  Simon Pilgrim authored Feb 08, 2022
  fd2bb51f
Feb 07, 2022
- [x86] avoid compile-time warning for parens; NFC · be059a12
  Sanjay Patel authored Feb 07, 2022
  
  be059a12
- [x86] avoid false dependency stall on 'sbb' with same source reg · 40a50f87
  Sanjay Patel authored Feb 07, 2022
  40a50f87
- [X86] combineShiftRightArithmetic - break if-else chain as they all return (style). NFC. · d7be2bff
  Simon Pilgrim authored Feb 07, 2022
  
  d7be2bff
- [llvm] Use = default (NFC) · 3a3cb929
  Kazu Hirata authored Feb 06, 2022
  
  3a3cb929
Feb 06, 2022
- [X86] Fold ZERO_EXTEND_VECTOR_INREG(BUILD_VECTOR(X,Y,?,?)) -> BUILD_VECTOR(X,0,Y,0) · 74b98ab1
  Simon Pilgrim authored Feb 06, 2022
  74b98ab1
Feb 05, 2022
- [X86] Introduce more common modern tunings into `generic` · 0b7669f3
  Phoebe Wang authored Feb 05, 2022
  0b7669f3