Commits · e021de0aab221beaa03f73821ab41850e9c1bdb8 · Roger Ferrer / llvm-epi · GitLab

Mar 11, 2021
- [PowerPC] Exploit paddi instruction on Power 10 for constant materialization · e021de0a
  Stefan Pintilie authored Mar 11, 2021
  e021de0a
- [PowerPC] Fix multi-use case for swap reduction · 72c4cbd6
  Qiu Chaofan authored Mar 11, 2021
  72c4cbd6
- [PowerPC] Fix infinite loop in peephole CR optimization (PR49509) · 2489cbaa
  Nikita Popov authored Mar 10, 2021
  2489cbaa
- [mir] Change 'undef' for MMO base addresses to 'unknown-address' · 134a179d
  Daniel Sanders authored Mar 05, 2021
  134a179d
Mar 10, 2021
- [PowerPC] Implement patterns for PC-Rel zextload/extload byte loads · 8b540c54
  Amy Kwan authored Mar 04, 2021
  8b540c54
- [NFC] [PowerPC] Remove unsafe-fp-math in some tests · e82a54ae
  Qiu Chaofan authored Mar 10, 2021
  e82a54ae
- [PowerPC] Reduce symmetrical swaps for lane-insensitive vector ops · 4c973ae5
  Qiu Chaofan authored Mar 10, 2021
  4c973ae5
Mar 09, 2021
- [P10] [Power PC] Exploiting new load rightmost vector element instructions. · 9b6ac9e9
  Albion Fung authored Mar 09, 2021
  9b6ac9e9
Mar 08, 2021
- [AIX][TLS] Generate 64-bit general-dynamic access code sequence · 535a4192
  Lei Huang authored Mar 05, 2021
  535a4192
- [PowerPC] Removing _massv place holder · 820f508b
  Masoud Ataei authored Mar 08, 2021
  820f508b
- [AIX][TLS] Generate 32-bit general-dynamic access code sequence · b0f01153
  Nemanja Ivanovic authored Mar 04, 2021
  b0f01153
- [PowerPC] Change target data layout for 16-byte stack alignment · acce4010
  Ahsan Saghir authored Feb 08, 2021
  acce4010
- [ConstantFold] allow folding icmp of null and constexpr · f75b5305
  Sanjay Patel authored Mar 08, 2021
  f75b5305
Mar 06, 2021
- [PowePC][AIX] Handle variadic vector call operands. · f0904a62
  Sean Fertile authored Mar 06, 2021
  f0904a62
Mar 05, 2021
- [PowerPC][AIX] Enable the default AltiVec ABI on AIX · 2b50ce15
  Zarko Todorovski authored Mar 05, 2021
  2b50ce15
Mar 04, 2021
- [mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero · 9fc2be6f
  Daniel Sanders authored Mar 02, 2021
  9fc2be6f
- [PowerPC][AIX] Handle variadic vector formal arguments. · aaeffbe0
  Sean Fertile authored Mar 04, 2021
  aaeffbe0
Mar 03, 2021
- [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness · 54c0f520
  Baptiste Saleil authored Mar 03, 2021
  54c0f520
- [PowerPC] Allow spilling GPR to VSR on AIX · 72d4a41b
  Qiu Chaofan authored Mar 03, 2021
  72d4a41b
- [AIX][TLS] Generate TLS variables in assembly files · 1756b2ad
  Victor Huang authored Mar 02, 2021
  1756b2ad
Mar 01, 2021
- Move EntryExitInstrumentation pass location · 040c1b49
  Arthur Eubanks authored Feb 26, 2021
  040c1b49
- [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. · e745f7c5
  Craig Topper authored Mar 01, 2021
  e745f7c5
- [PowerPC] Removing sqrtd2 and sqrtf4 from list of vectorizable function with MASSV · 5fe0cab7
  Masoud Ataei authored Mar 01, 2021
  5fe0cab7
Feb 27, 2021
- ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects · 47c5576d
  Fangrui Song authored Feb 26, 2021
  47c5576d
Feb 25, 2021
- [NFC][AIX] Rename aix-csr-vector.ll to aix-csr-vector-extabi.ll · 1c051b7b
  Zarko Todorovski authored Feb 24, 2021
  
  1c051b7b
Feb 24, 2021
- [XCOFF] add C_FILE symbol at index 0 of symbol table. · 71a39862
  Chen Zheng authored Feb 23, 2021
  71a39862
Feb 18, 2021
- [PowerPC][AIX] Add support for vector arg passing on the stack. · bb260b1c
  Sean Fertile authored Feb 18, 2021
  bb260b1c
- [PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10 · 34dc1ccb
  Baptiste Saleil authored Feb 17, 2021
  34dc1ccb
- [PowerPC] Add option for ROP Protection · b80357d4
  Stefan Pintilie authored Feb 18, 2021
  b80357d4
Feb 17, 2021
- [PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX. · cb287680
  Sidharth Baveja authored Feb 17, 2021
  cb287680
- [PowerPC] Handle FP physical register in inline asm constraint. · 4e127bce
  Sean Fertile authored Feb 17, 2021
  4e127bce
Feb 13, 2021
- [test] Make ELF tests less reliant on the lexicographical order of non-local symbols · 39db16e7
  Fangrui Song authored Feb 13, 2021
  
  39db16e7
Feb 11, 2021
- [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on... · 5744502a
  Craig Topper authored Feb 11, 2021
  5744502a
Feb 09, 2021
- [DAGCombine] Do not remove masking argument to FP16_TO_FP for some targets · a5222aa0
  Nemanja Ivanovic authored Feb 09, 2021
  a5222aa0
Feb 02, 2021
- [PowerPC] Materialize 34 bit constants with pli on Power 10. · 288f762b
  Stefan Pintilie authored Feb 02, 2021
  288f762b
Jan 28, 2021
- [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases · 2e470e03
  Albion Fung authored Jan 28, 2021
  2e470e03
- [PowerPC] Do not emit XXSPLTI32DX for sub 64-bit constants · 54e570d9
  Nemanja Ivanovic authored Jan 27, 2021
  54e570d9
Jan 26, 2021
- [PowerPC] Do not emit HW loop with half precision operations · 8018f731
  Nemanja Ivanovic authored Jan 25, 2021
  8018f731
Jan 25, 2021
- [PowerPC] Add missing negate for VPERMXOR on little endian subtargets · 1150bfa6
  Nemanja Ivanovic authored Jan 25, 2021
  1150bfa6
- [PowerPC] support register pressure reduction in machine combiner. · 0ed4cf4b
  Chen Zheng authored Jan 17, 2021
  0ed4cf4b