Commits · e2926501d886ce8c1cd08db1d3a02c314c2f412d · Roger Ferrer / llvm-epi · GitLab

May 18, 2022
- [SelectionDAGBuilder] Pass fast math flags to most of VP SDNodes. · 00999fb6
  Yeting Kuo authored May 14, 2022
  00999fb6
May 17, 2022
- [RISCV] Add additional test coverage of 11a7e77c and related transforms · a5983e57
  Philip Reames authored May 17, 2022
  
  a5983e57
- [RISCV] Canonicalize AVL=setvli to AVL=Imm or AVL=VLMAX · 11a7e77c
  Philip Reames authored May 17, 2022
  11a7e77c
- [RISCV] Add a test showing incorrect RVV stack alignment · f7709a05
  Fraser Cormack authored Oct 01, 2021
  f7709a05
- [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses · d40b7f0d
  Simon Pilgrim authored May 17, 2022
  d40b7f0d
- [SelectionDAG] Support more VP reduction mask operation. · 26593e73
  Jianjian GUAN authored May 05, 2022
  26593e73
- [RISCV] Add a test w/ RVV stack objects misaligning non-RVV ones · 821522d3
  Fraser Cormack authored May 11, 2022
  821522d3
- [StackColoring] Don't merge slots with differing StackIDs · 599ff247
  Fraser Cormack authored May 16, 2022
  599ff247
- [RISCV] Use classic dataflow for VSETVLI insertion · 14748803
  Philip Reames authored May 16, 2022
  14748803
- [RISCV] Fix missing vsetvli in transparent block case · 3d17c917
  Philip Reames authored May 16, 2022
  3d17c917
- Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV) · 7dbf2e7b
  Philip Reames authored May 16, 2022
  7dbf2e7b
May 16, 2022
- [AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC · 74f6ded4
  Craig Topper authored May 16, 2022
  74f6ded4
- [TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift. · 1c4880a2
  Craig Topper authored May 16, 2022
  1c4880a2
- [RISCV] Fix incorrect use of tail agnostic vslideup. · 1878f240
  Zakk Chen authored May 15, 2022
  1878f240
May 15, 2022
- [RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC · d0312a5c
  Craig Topper authored May 14, 2022
  d0312a5c
- [RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC · c748d2cd
  Craig Topper authored May 14, 2022
  c748d2cd
May 14, 2022
- [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits · 1ecc3d86
  Simon Pilgrim authored May 14, 2022
  1ecc3d86
- [RISCV] Use the new chain when converting a fixed RVV load · 189ca695
  Roger Ferrer authored May 13, 2022
  189ca695
- [RISCV][NFC] Test showing wrong scheduling of expansion of memmove for fixed RVV · fc9bed02
  Roger Ferrer authored May 13, 2022
  fc9bed02
May 13, 2022
- Revert "[RISCV] Enable subregister liveness tracking for RVV." · a2918976
  Craig Topper authored May 13, 2022
  a2918976
- [RISCV] Precommit tests showing missed vlenb optimizations · 0513502a
  Philip Reames authored May 13, 2022
  
  0513502a
- [RISCV] Add llvm.read.register support for vlenb · af5e09b7
  Philip Reames authored May 13, 2022
  af5e09b7
- [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics. · 7dfc56c1
  Zakk Chen authored May 10, 2022
  7dfc56c1
- [LegalizeTypes][VP] Add integer promotion support for vp.setcc · 693758b2
  Lian Wang authored May 12, 2022
  693758b2
- [LegalizeTypes][VP] Add integer promotion support for vp.merge · 8050ba66
  Lian Wang authored May 12, 2022
  8050ba66
May 12, 2022
- [RISCV] Extend dataflow workaround from D119518 to fallthrough blocks · 52b5f1f7
  Philip Reames authored May 12, 2022
  52b5f1f7
- [RISCV] Use tail agnostic policy when selecting riscv_fma_vl to instructions · 40e96545
  Craig Topper authored May 11, 2022
  40e96545
- [LegalizeVectorTypes] Enable WidenVecRes_SETCC work for scalable vector. · 9176096c
  Lian Wang authored May 12, 2022
  9176096c
- [RISCV][NFC] Simplify tests by reorganizing check prefixes · 995d3892
  Ping Deng authored May 12, 2022
  995d3892
May 11, 2022
- [riscv] Add a bunch of tests exploring switch lowering · 4c4c5511
  Philip Reames authored May 11, 2022
  4c4c5511
- [RISCV] Enable subregister liveness tracking for RVV. · ed242b54
  Craig Topper authored May 11, 2022
  ed242b54
- [RISCV] Fold addiw from (add X, (addiw (lui C1, C2))) into load/store address · 5c7ec998
  Craig Topper authored May 11, 2022
  5c7ec998
- [test, riscv] Add test illustrating missing handling for fallthrough blocks in 541c9ba8 · ca81c0f8
  Philip Reames authored May 11, 2022
  
  ca81c0f8
- [RISCV] Add caching to the gather/scatter to strided load/store conversion. · f499ec6b
  Craig Topper authored May 11, 2022
  f499ec6b
- [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. · 0ebb02b9
  Craig Topper authored May 11, 2022
  0ebb02b9
- [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64. · 07817427
  Craig Topper authored May 11, 2022
  07817427
- [riscv] Canonicalize vsetvli (vsetvli avl, vtype1) vtype2 transitionsas reviewed · 72925d98
  Philip Reames authored May 11, 2022
  72925d98
- [riscv] Add tests for vsetvli reuse across iterations of a loop · 98736234
  Philip Reames authored May 11, 2022
  98736234
- [RISCV] Remove some TODOs in tests · b049eb1f
  Shao-Ce SUN authored May 10, 2022
  b049eb1f
- [riscv] Prefer to use previous VL for scalar move instructionsK · cc0283a6
  Philip Reames authored May 11, 2022
  cc0283a6