Commits · e3fa2b1eab60342dc882b7b888658b03c472fa2b · Roger Ferrer / llvm-epi · GitLab

Jul 16, 2021
- Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID" · e3fa2b1e
  Fraser Cormack authored Jul 16, 2021
  e3fa2b1e
- [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID · a6ca88e9
  Fraser Cormack authored Jun 24, 2021
  a6ca88e9
Jul 14, 2021
- [RISCV] Fix the neutral element in vector 'fadd' reductions · 03a4702c
  Fraser Cormack authored Jul 13, 2021
  03a4702c
Jul 13, 2021
- [RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant. · 1e670dc7
  Craig Topper authored Jul 13, 2021
  1e670dc7
- [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. · 46e89708
  Craig Topper authored Jul 12, 2021
  46e89708
- [RISCV] Support machine constraint "S" · 3d89fb4d
  Fangrui Song authored Jul 13, 2021
  3d89fb4d
- [RISCV] Pass undef VECTOR_SHUFFLE indices on to BUILD_VECTOR · d991b721
  Fraser Cormack authored Jun 23, 2021
  d991b721
Jul 12, 2021
- [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. · ec1cdee6
  Eli Friedman authored Jul 12, 2021
  ec1cdee6
Jul 11, 2021
- [RISCV] Add tests for suboptimal handling of negative constants for i32 uaddo/usubo on RV64. NFC · f0393deb
  Craig Topper authored Jul 11, 2021
  f0393deb
- [RISCV] Add tests for suboptimal handling of negative constants on the LHS of... · 6644a611
  Craig Topper authored Jul 11, 2021
  6644a611
- [RISCV] Remove stale FIXME from a test. NFC · 1410aab6
  Craig Topper authored Jul 11, 2021
  1410aab6
- [RISCV] Restore non-constant srem test I accidentally deleted. NFC · 99b8c468
  Craig Topper authored Jul 10, 2021
  
  99b8c468
- [RISCV] Add test cases for div/rem with constant left hand side. NFC · 86109fa9
  Craig Topper authored Jul 10, 2021
  86109fa9
Jul 09, 2021
- [RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD · ed102ce2
  Ben Shi authored Jul 09, 2021
  ed102ce2
Jul 06, 2021
- [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno · 12d51f95
  Craig Topper authored Jul 06, 2021
  12d51f95
- [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors. · 2b5e5311
  Craig Topper authored Jul 06, 2021
  2b5e5311
Jun 30, 2021
- CodeGen: Print/parse LLTs in MachineMemOperands · fae05692
  Matt Arsenault authored May 19, 2021
  fae05692
Jun 29, 2021
- [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being... · 3b6dfa38
  Craig Topper authored Jun 28, 2021
  3b6dfa38
Jun 27, 2021
- [RISCV] Add tests for __builtin_parity idiom. · 4c92e31d
  Craig Topper authored Jun 27, 2021
  4c92e31d
- Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve... · 010f0f00
  Craig Topper authored Jun 27, 2021
  010f0f00
Jun 26, 2021
- [RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions. · 81b2f959
  Craig Topper authored Jun 26, 2021
  
  81b2f959
- [RISCV] Add DAG combine to detect opportunities to replace (i64 (any_extend... · d4f4a1ba
  Craig Topper authored Jun 25, 2021
  d4f4a1ba
Jun 25, 2021
- [RISCV] Permit larger RVV stacks and stack offsets · ab1bd255
  Fraser Cormack authored Jun 22, 2021
  ab1bd255
Jun 24, 2021
- [RISCV] Lower RVV vector SELECTs to VSELECTs · a4729f7f
  Fraser Cormack authored Jun 23, 2021
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- [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt. · 91319534
  Craig Topper authored Jun 23, 2021
  91319534
Jun 23, 2021
- [Verifier] Fail on overrunning and invalid indices for {insert,extract} vector intrinsics · 3c4dbf6e
  Joe Ellis authored Jun 18, 2021
  3c4dbf6e
Jun 21, 2021
- [RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul. · 9080659a
  Craig Topper authored Jun 21, 2021
  9080659a
Jun 19, 2021
- [RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi. · b663f30f
  Craig Topper authored Jun 19, 2021
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- [RISCV] Optimize add-mul in the zba extension with SH*ADD · d934b728
  Ben Shi authored Jun 19, 2021
  d934b728
- [RISCV][test] Add new tests for add-mul optimization in the zba extension with SH*ADD · 31190738
  Ben Shi authored Jun 19, 2021
  31190738
Jun 18, 2021
- [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL... · ac87133f
  Craig Topper authored Jun 18, 2021
  ac87133f
Jun 17, 2021
- test: clean up some of the RISCV tests (NFC) · e70d4994
  Saleem Abdulrasool authored Jun 17, 2021
  e70d4994
- RISCV: adjust handling of relocation emission for RISCV · bbea6425
  Saleem Abdulrasool authored May 26, 2021
  bbea6425
- [RISCV][VP] Lower FP VP ISD nodes to RVV instructions · fed1503e
  Fraser Cormack authored Jun 14, 2021
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- Update @llvm.powi to handle different int sizes for the exponent · 4c7f820b
  Bjorn Pettersson authored Mar 26, 2021
  4c7f820b
- [RISCV][test] Add new tests of SH*ADD in the zba extension · 07990571
  Ben Shi authored Jun 17, 2021
  07990571
Jun 14, 2021
- [RISCV] Transform unaligned RVV vector loads/stores to aligned ones · c75e454c
  Fraser Cormack authored Jun 09, 2021
  c75e454c
Jun 11, 2021
- [RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects. · 643b6407
  Hsiangkai Wang authored Jun 03, 2021
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- [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. · 420bd5ee
  Craig Topper authored Jun 10, 2021
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- [RISCV] Add test cases that show failure to use some W instructions if they... · b35a8425
  Craig Topper authored Jun 10, 2021
  b35a8425