Commits · e433ca28ec923929efe4f6babb8d33b4e6673ac1 · Roger Ferrer / llvm-epi · GitLab

Jan 13, 2021
- [AArch64][GlobalISel] Add support for FCONSTANT of FP128 type · 4e8e8889
  Muhammad Asif Manzoor authored Jan 13, 2021
  4e8e8889
- [NFC][RISCV] Add double type in RISC-V V CodeGen test cases for RV32. · 350c0552
  Hsiangkai Wang authored Jan 13, 2021
  350c0552
- GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper · d55d592a
  Matt Arsenault authored Aug 19, 2020
  d55d592a
- [AArch64] Attempt to sink mul operands · dda60035
  Nicholas Guy authored Dec 02, 2020
  dda60035
- [X86] Add tests for rv_marker lowering. · b7b1e8c3
  Florian Hahn authored Jan 13, 2021
  b7b1e8c3
- [SVE][CodeGen] CTLZ, CTTZ & CTPOP operations (predicates) · 2170e0ee
  Kerry McLaughlin authored Jan 13, 2021
  2170e0ee
- [SVE] Add ISel pattern for addvl · ad85e396
  Cullen Rhodes authored Jan 12, 2021
  ad85e396
- [X86][AVX] combineVectorSignBitsTruncation - limit AVX512 truncations to 128-bits (PR48727) · 0f59d099
  Simon Pilgrim authored Jan 13, 2021
  0f59d099
- [AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics · 3122c66a
  Joe Ellis authored Jan 11, 2021
  3122c66a
- [ARM] Update isVMOVNOriginalMask to handle single input shuffle vectors · c29ca855
  David Green authored Jan 13, 2021
  c29ca855
- [ARM] Additional tests for different interleaving patterns. NFC · 3aeb30d1
  David Green authored Jan 13, 2021
  
  3aeb30d1
- [Verifier] Extend statepoint verifier to cover more constants · fba9805b
  Serguei Katkov authored Jan 12, 2021
  fba9805b
- [AMDGPU] Add SI_EARLY_TERMINATE_SCC0 for early terminating shader · 790c75c1
  Carl Ritson authored Jan 13, 2021
  790c75c1
- [NFC] Use generic name for scalable vector stack ID. · 914e2f5a
  Hsiangkai Wang authored Jan 12, 2021
  914e2f5a
- [DAGCombiner] Fold BRCOND(FREEZE(COND)) to BRCOND(COND) · 25eb7b08
  Juneyoung Lee authored Jan 13, 2021
  25eb7b08
- [AMDGPU] Add _e64 suffix to VOP3 Insts · 314e29ed
  Joe Nash authored Jan 07, 2021
  314e29ed
Jan 12, 2021
- [RISCV] Remove '.mask' from vcompress intrinsic name. NFC · 1730b0f6
  Craig Topper authored Jan 12, 2021
  1730b0f6
- AMDGPU: Remove wrapper only call limitation · 3d397091
  Matt Arsenault authored Jan 06, 2021
  3d397091
- [AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly · d1fa7afc
  Martin Storsjö authored Dec 11, 2020
  d1fa7afc
- [RISCV] Legalize select when Zbt extension available · 71ed4b6c
  Michael Munday authored Jan 12, 2021
  71ed4b6c
- [RISCV] Add double test cases to vfmerge-rv32.ll. NFC · 7583ae48
  Craig Topper authored Jan 12, 2021
  
  7583ae48
- [clang][aarch64] Precondition isHomogeneousAggregate on isCXX14Aggregate · e5f51fdd
  David Truby authored Dec 03, 2020
  e5f51fdd
- [RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand. · a14040bd
  Craig Topper authored Jan 12, 2021
  a14040bd
- [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of... · 03c8d6a0
  Craig Topper authored Jan 12, 2021
  03c8d6a0
- [SVE][NFC] Regenerate a few CodeGen tests · 3d9c51d1
  Cullen Rhodes authored Jan 12, 2021
  3d9c51d1
- [AMDGPU] Regenerate umax crash test · a4931d4f
  Simon Pilgrim authored Jan 12, 2021
  
  a4931d4f
- [X86] Regenerate sdiv_fix_sat.ll + udiv_fix_sat.ll tests · 85aaa3e3
  Simon Pilgrim authored Jan 12, 2021
  85aaa3e3
- [PowerPC] Add support for embedded devices with EFPU2 · 3f7b4ce9
  Nemanja Ivanovic authored Jan 12, 2021
  3f7b4ce9
- [VE] Update VELIntrinsic tests · 24faa870
  Kazushi (Jam) Marukawa authored Jan 12, 2021
  24faa870
- [X86] Improved lowering for saturating float to int. · 07605ea1
  Bevin Hansson authored Jan 12, 2021
  07605ea1
- [X86][SSE] getFauxShuffleMask - handle PACKSS(SRAI(),SRAI()) shuffle patterns. · 2ed914cb
  Simon Pilgrim authored Jan 12, 2021
  2ed914cb
- [X86][SSE] combineSubToSubus - add v16i32 handling on pre-AVX512BW targets. · 7e442081
  Simon Pilgrim authored Jan 12, 2021
  7e442081
- [X86][SSE] combineSubToSubus - remove SSE2 early-out. · a5212b5c
  Simon Pilgrim authored Jan 12, 2021
  a5212b5c
- [RISCV] Improve scalable-vector shift tests (NFC) · 09db958e
  Fraser Cormack authored Jan 08, 2021
  09db958e
- [AMDGPU][GlobalISel] Remove some duplicate RUN lines · 794e3d94
  Jay Foad authored Aug 26, 2020
  794e3d94
- [WebAssembly] Remove more unnecessary brs in CFGStackify · c93b9559
  Heejin Ahn authored Dec 28, 2020
  c93b9559
- [AMDGPU] Fix failing assert with scratch ST mode · 6a195491
  Sebastian Neubauer authored Jan 11, 2021
  6a195491
- [CodeGen] Try to make the print of memory operand alignment a little more user friendly. · b1c304c4
  Craig Topper authored Jan 11, 2021
  b1c304c4
- [WebAssembly] Ensure terminate pads are a single BB · 9f8b2576
  Heejin Ahn authored Dec 27, 2020
  9f8b2576
- [RISCV] Define the vfclass RVV intrinsics · 7470017f
  Evandro Menezes authored Dec 30, 2020
  7470017f