Commits · e637feee80f94d23950d25673b6c2e0d46d335a9 · Roger Ferrer / llvm-epi · GitLab

Jul 29, 2022
- [RISCV] Add isel pattern for (setne/eq GPR, -2048) · e637feee
  Craig Topper authored Jul 29, 2022
  e637feee
- [AMDGPU] Omit unnecessary waitcnt before barriers · 2c82a126
  Austin Kerbow authored Feb 24, 2022
  2c82a126
- [AArch64][SVE] Change DupLane128Combine Index comparison to 0 · a8b726ac
  Matt Devereau authored Jul 29, 2022
  a8b726ac
- [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X) (REAPPLIED) · bc2c4f6c
  Simon Pilgrim authored Jul 29, 2022
  bc2c4f6c
- [AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11 · 6a1aa627
  Mirko Brkusanin authored Jul 29, 2022
  6a1aa627
- [AMDGPU] user-sgpr-init16-bug does not apply to gfx1103 · 3cfa9b14
  Jay Foad authored Jul 22, 2022
  3cfa9b14
- AMDGPU: Fix assertion when printing unreachable functions · ef906f28
  Matt Arsenault authored Jul 24, 2022
  ef906f28
- Revert "[AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs" · d7ae1a90
  Alexander Timofeev authored Jul 29, 2022
  d7ae1a90
- [LoongArch] Offset folding for frameindex · 56ab2f4c
  wanglei authored Jul 29, 2022
  56ab2f4c
- [LoongArch] Refactor insertDivByZeroTrap · fd654532
  wanglei authored Jul 29, 2022
  fd654532
- [AArch64][DAGCombine] Add performBuildVectorCombine 'extract_elt ~> anyext' · 487fa6f8
  David Sherwood authored Jul 29, 2022
  487fa6f8
- AMDGPU: Take care of "tied" operand when removeOperand · 2b731b30
  Changpeng Fang authored Jul 28, 2022
  2b731b30
Jul 28, 2022
- [AMDGPU][Scheduler] Avoid initializing Register pressure tracker when tracking is disabled · 5c380564
  Anshil Gandhi authored Jul 28, 2022
  5c380564
- [AMDGPU] Add isMeta flag to SCHED_GROUP_BARRIER · 0f93a45b
  Austin Kerbow authored Jul 28, 2022
  
  0f93a45b
- [AMDGPU] Add amdgcn_sched_group_barrier builtin · f5b21680
  Austin Kerbow authored Jun 13, 2022
  f5b21680
- [RISCV] Update lowerFROUND to use masked instructions. · 2750873d
  Craig Topper authored Jul 28, 2022
  2750873d
- [RISCV] Remove duplicate code. NFC · 89173dee
  Craig Topper authored Jul 28, 2022
  89173dee
- Revert "[X86][DAGISel] Don't widen shuffle element with AVX512" · f912bab1
  Florian Hahn authored Jul 28, 2022
  f912bab1
- [AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs · 76d9ae92
  Alexander Timofeev authored Jul 26, 2022
  76d9ae92
- [AMDGPU][MC][GFX90A] Correct MIMG dst size validation · 2b230d69
  Dmitry Preobrazhensky authored Jul 28, 2022
  2b230d69
- [AMDGPU][MC][GFX11] Disable SGPRs for src1 of v_fma_mix*_dpp opcodes · fa7fd8ec
  Dmitry Preobrazhensky authored Jul 28, 2022
  fa7fd8ec
- [Aarch64] Add cost for missing extensions. · 7eeb468a
  chendewen authored Jul 28, 2022
  7eeb468a
- [X86][MC] Avoid emitting incorrect warning for complex FMUL · 726d9f8e
  Phoebe Wang authored Jul 28, 2022
  726d9f8e
- [AMDGPU] Aggressively schedule to reduce RP in occupancy limited regions · ba0d079c
  Austin Kerbow authored Jul 19, 2022
  ba0d079c
- [AArch64][GlobalISel] Fix custom legalization of rotates using sext for shift vs zext. · 93e3aeb9
  Amara Emerson authored Jul 27, 2022
  93e3aeb9
- [AMDGPU][SIFoldOperands] Clear kills when folding COPY · dbda30e2
  Carl Ritson authored Jul 28, 2022
  dbda30e2
- [RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI. · a304d70e
  Craig Topper authored Jul 27, 2022
  a304d70e
- [RISCV] Reorder code in lowerFROUND to make the diff in D130659 cleaner. NFC · 1d1d8d60
  Craig Topper authored Jul 27, 2022
  
  1d1d8d60
- [RISCV] Add merge operand to RISCVISD::FCOPYSIGN_VL. · 98647330
  Craig Topper authored Jul 27, 2022
  98647330
Jul 27, 2022
- Revert "[llvm][NFC] Refactor code to use ProfDataUtils" · 6e9bab71
  Paul Kirth authored Jul 27, 2022
  6e9bab71
- [llvm][NFC] Refactor code to use ProfDataUtils · 300c9a78
  Paul Kirth authored Jun 29, 2022
  300c9a78
- [RISCV] Enable (scalable) vectorization by default · 15c645f7
  Philip Reames authored Jul 27, 2022
  15c645f7
- [AMDGPU] Consider S_SETPRIO a scheduling boundary · 68901fdb
  Stanislav Mekhanoshin authored Jul 27, 2022
  68901fdb
- Use hasNItemsOrLess() in MRI::hasAtMostUserInstrs(). · 65246d3e
  Amara Emerson authored Jul 27, 2022
  
  65246d3e
- [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.pmull64 · 34348814
  Mingming Liu authored Jul 25, 2022
  34348814
- [AArch64][GlobalISel] Add heuristics for localizing G_CONSTANT. · 19cdd190
  Amara Emerson authored Jul 26, 2022
  19cdd190
- Fix misc uses of "long" variables to use "int64_t". · 1a6d82b9
  Eli Friedman authored Jul 27, 2022
  1a6d82b9
- [RISCV] Add isel pattern for (mul (and X, 0xffffffff), 3<<C) with Zba. · 32622d6d
  Craig Topper authored Jul 27, 2022
  32622d6d
- [RISCV] Disable constant hoisting for multiply by negated power of 2. · 9b27d132
  Craig Topper authored Jul 27, 2022
  9b27d132
- [PowerPC] Change long to int64_t (which is always 64 bit or 8 bytes ) · f38ea84a
  Umesh Kalappa authored Jul 27, 2022
  f38ea84a