Commits · e7a306310b0bfbd97cdce8f77686b6453fc76bca · Roger Ferrer / llvm-epi · GitLab

Dec 30, 2022
- [AMDGPU][GFX11] Correct tied src2 of v_fmac_f16_e64 · e7a30631
  Dmitry Preobrazhensky authored Dec 30, 2022
  e7a30631
- AMDGPU: Use default attributes on image dim intrinsics · 3eecc838
  Matt Arsenault authored Dec 30, 2022
  3eecc838
- [AMDGPU][MC][GFX11] Correct encoding of neg modifier for v_dot2_f32_bf16 · 9f40d9ff
  Dmitry Preobrazhensky authored Dec 30, 2022
  9f40d9ff
- [NFC][IR] Remove unused assignment to Offset · dd50e26f
  Alfonso Gregory authored Sep 21, 2021
  dd50e26f
- [ScheduleDAG] Support REQ_SEQUENCE unscheduling · 98265db8
  Filipp Zhinkin authored Dec 27, 2022
  98265db8
- [CodeGen] Temporarily disable-lsr in HWASAN build · 8f70b848
  Vitaly Buka authored Dec 29, 2022
  8f70b848
- [RISCV] Use SUB instead of XOR in lowerShiftLeftParts/lowerShiftRightParts./ · a63b7247
  Craig Topper authored Dec 29, 2022
  a63b7247
- [RISCV] RISCVDAGToDAGISel::selectShiftMask to shift by (sub size-1, X). · 7cd72585
  Craig Topper authored Dec 29, 2022
  7cd72585
- AMDGPU/clang: Remove target features from address space test builtins · e630d9b2
  Matt Arsenault authored Nov 28, 2022
  e630d9b2
- DAG: Prevent store value forwarding to distinct addrspace load · 0ec51a46
  Dmitry Borisenkov authored Dec 29, 2022
  0ec51a46
- [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to bypass adds with constant. · e50976e5
  Craig Topper authored Dec 29, 2022
  e50976e5
Dec 29, 2022
- [NFC][Codegen][X86] zero_extend_vector_inreg.ll: add SSE4.2 runline · c823517e
  Roman Lebedev authored Dec 30, 2022
  
  c823517e
- [DAGCombiner] Try to partition ISD::EXTRACT_VECTOR_ELT to accomodate it's ISD::BUILD_VECTOR users · 248567a3
  Roman Lebedev authored Dec 29, 2022
  248567a3
- [TargetLowering] Teach BuildUDIV to take advantage of leading zeros in the dividend. · 8abd7008
  Craig Topper authored Dec 29, 2022
  8abd7008
- [instrprof] Fix issue in binary-ids-padding.test · 1ec02146
  Gulfem Savrun Yeniceri authored Dec 29, 2022
  1ec02146
- [ProfileData] Fix msan -fsanitize-memory-param-retval after D135929 · 484f69ba
  Fangrui Song authored Dec 29, 2022
  484f69ba
- [llvm][AsmPrinter][NFC] Cleanup `GCMetadataPrinters` field · 8f8313d5
  Markus Böck authored Dec 29, 2022
  8f8313d5
- [InstCombine] avoid miscompile in sinkNotIntoLogicalOp() · 30af2e31
  Sanjay Patel authored Dec 29, 2022
  30af2e31
- [InstCombine] add test for miscompile from sinkNotIntoLogicalOp(); NFC · e5a73098
  Sanjay Patel authored Dec 29, 2022
  e5a73098
- [SLP] Fix debug print for cost in tryToVectorizeList - NFC. · ad956ed5
  Valery N Dmitriev authored Dec 29, 2022
  ad956ed5
- [BPF] Use SectionForGlobal() for section names computation in BTF · ed068386
  Eduard Zingerman authored Dec 29, 2022
  ed068386
- [SLP] A couple of minor improvements for slp graph view - NFC. · 8eb3698b
  Valery N Dmitriev authored Dec 29, 2022
  8eb3698b
- [profile] Add binary ids into indexed profiles · 1ae7d838
  Gulfem Savrun Yeniceri authored Oct 13, 2022
  1ae7d838
- [Support] Fix what I think is an off by 1 bug in UnsignedDivisionByConstantInfo. · 1490796d
  Craig Topper authored Dec 29, 2022
  1490796d
- [InstSimplify] fold exact divide to poison if it is known to not divide evenly · f0faea57
  Sanjay Patel authored Dec 29, 2022
  f0faea57
- Detemplate llvm::EmitGEPOffset and move it into a cpp file. NFC. · a3d58bba
  Benjamin Kramer authored Dec 29, 2022
  
  a3d58bba
- [MC] [llvm-ml] Add support for the extrn keyword · a0b7bd4b
  Mike Hommey authored Dec 29, 2022
  a0b7bd4b
- [InstSimplify] fix formatting and add bool function argument comments; NFC · b16d04d2
  Sanjay Patel authored Dec 29, 2022
  b16d04d2
- [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative · af5dd270
  Hsiangkai Wang authored Dec 23, 2022
  af5dd270
- [RISCV] Add integer scalar instructions to isAssociativeAndCommutative · 002005e6
  Hsiangkai Wang authored Dec 22, 2022
  002005e6
- [InstCombine] Fold (X << Z) / (X * Y) -> (1 << Z) / Y · 1f84e72b
  Chenbing Zheng authored Dec 29, 2022
  1f84e72b
- [RISCV] Add Svpbmt extension support. · bd9c0f08
  Yeting Kuo authored Dec 27, 2022
  bd9c0f08
- [RISCV] Add SH1ADD/SH2ADD/SH3ADD to RISCVDAGToDAGISel::hasAllNBitUsers. · 0e9855c1
  Craig Topper authored Dec 28, 2022
  
  0e9855c1
- [RISCV] Prefer ADDI over ORI if the known bits are disjoint. · 79d6e9c7
  Craig Topper authored Dec 28, 2022
  79d6e9c7
- [DFSan] Add `zeroext` attribute for callbacks with 8bit shadow variable arguments · 14ce567f
  Weining Lu authored Dec 29, 2022
  14ce567f
- [NFC][Codegen][X86] Add exhaustive-ish test coverage for ZERO_EXTEND_VECTOR_INREG · 778a7df5
  Roman Lebedev authored Dec 29, 2022
  778a7df5
- [RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC · 9b59207a
  Craig Topper authored Dec 28, 2022
  9b59207a
- [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers. · 6357b637
  Craig Topper authored Dec 28, 2022
  
  6357b637
Dec 28, 2022
- [RISCV] Support SRLI in hasAllNBitUsers. · cdf09ce7
  Craig Topper authored Dec 28, 2022
  cdf09ce7
- [RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC · ac51cf19
  Craig Topper authored Dec 28, 2022
  ac51cf19