Commits · e7d97368f2d862bc6b4d792ebafaaf19103ae403 · Roger Ferrer / llvm-epi · GitLab

Nov 03, 2016
- Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently" · e7d97368
  James Molloy authored Nov 03, 2016
  e7d97368
- [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently · b60d8b19
  James Molloy authored Nov 03, 2016
  b60d8b19
- [AVX-512] Use 'vnot' instead of 'not' in patterns involving vXi1 vectors. · 7b9cc147
  Craig Topper authored Nov 03, 2016
  7b9cc147
- Expandload and Compressstore intrinsics · caaceef4
  Elena Demikhovsky authored Nov 03, 2016
  caaceef4
Nov 02, 2016
- [Hexagon] Remove registers coalesced in expand-condsets from live intervals · ead77016
  Krzysztof Parzyszek authored Nov 02, 2016
  ead77016
- AMDGPU: Allow additional implicit operands on MOVRELS instructions · 368972c3
  Nicolai Haehnle authored Nov 02, 2016
  368972c3
- Fix Clang-tidy readability-redundant-string-cstr warnings · 06ac79c2
  Malcolm Parsons authored Nov 02, 2016
  06ac79c2
- [ARM][MC] Cleanup ARM Target Assembly Parser · 0a392a8e
  Nirav Dave authored Nov 02, 2016
  0a392a8e
- [mips] Always run the MipsOptimizePICCall pass. · e3bb72ea
  Vasileios Kalintiris authored Nov 02, 2016
  e3bb72ea
- Create the virtual register for the global base in the intersection of · bef3621a
  Joerg Sonnenberger authored Nov 02, 2016
  bef3621a
- Removing a switch statement that contains a default label, but no case labels.... · 3ac3a7ef
  Aaron Ballman authored Nov 02, 2016
  3ac3a7ef
- [SystemZ] Fix compiler warnings introduced by r285574 · 75d2f1b1
  Ulrich Weigand authored Nov 02, 2016
  75d2f1b1
- [llvm] FIx if-clause -Wmisleading-indentation issue. · 1f175118
  Kirill Bobyrev authored Nov 02, 2016
  1f175118
- [AVR] Add instruction selection lowering code · 7549b0a0
  Dylan McKay authored Nov 02, 2016
  7549b0a0
- Support: Remove MemoryObject and DataStreamer interfaces. · 4e76019e
  Peter Collingbourne authored Nov 02, 2016
  4e76019e
- [RISCV] Add bare-bones RISC-V MCTargetDesc · 6b2cca7f
  Alex Bradbury authored Nov 01, 2016
  6b2cca7f
- [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td · 24d9b13b
  Alex Bradbury authored Nov 01, 2016
  24d9b13b
- AMDGPU: Handle CopyToReg in getOperandRegClass · c507cdb4
  Matt Arsenault authored Nov 01, 2016
  c507cdb4
- AMDGPU: Use brev for materializing SGPR constants · 663ab8c1
  Matt Arsenault authored Nov 01, 2016
  663ab8c1
Nov 01, 2016
- AMDGPU: Default to using scalar mov to materialize immediate · 3d463193
  Matt Arsenault authored Nov 01, 2016
  3d463193
- AMDGPU: Stop creating unused virtual registers · a6319b82
  Matt Arsenault authored Nov 01, 2016
  a6319b82
- AMDGPU: Workaround for instruction size with literals · 2d8c289b
  Matt Arsenault authored Nov 01, 2016
  2d8c289b
- [Hexagon] Rename operand/predicate names for unshifted integers · 654dc11b
  Krzysztof Parzyszek authored Nov 01, 2016
  654dc11b
- [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32 · d971a112
  Konstantin Zhuravlyov authored Nov 01, 2016
  d971a112
- [RISCV] Add stub backend · b2e5472d
  Alex Bradbury authored Nov 01, 2016
  b2e5472d
- AMDGPU: Fix buildbots broken by r285704 · 9677b602
  Tom Stellard authored Nov 01, 2016
  9677b602
- [TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h · 58eba099
  Alex Bradbury authored Nov 01, 2016
  58eba099
- AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64 · 94c21bc0
  Tom Stellard authored Nov 01, 2016
  94c21bc0
- [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables · 70a3d6df
  James Molloy authored Nov 01, 2016
  70a3d6df
- [AMDGPU] Expand vector mulhu/mulhs · 8a89d366
  Valery Pykhtin authored Nov 01, 2016
  8a89d366
- [PowerPC] Implement vector shift builtins - llvm portion · e70fa633
  Nemanja Ivanovic authored Nov 01, 2016
  e70fa633
- AMDGPU: Whitespace fixes · f3dd8630
  Matt Arsenault authored Nov 01, 2016
  f3dd8630
Oct 31, 2016
- [Hexagon] Garbage collect dead code. · 51cbe13a
  Davide Italiano authored Oct 31, 2016
  51cbe13a
- CodeGen: further loosen -O0 CG for WoA division · e1aa782b
  Saleem Abdulrasool authored Oct 31, 2016
  e1aa782b
- [NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass. · ed1e312f
  Justin Lebar authored Oct 31, 2016
  ed1e312f
- [PPC] add absolute difference altivec instructions and matching intrinsics · 60bdfe5a
  Nemanja Ivanovic authored Oct 31, 2016
  60bdfe5a
- GlobalISel: allow truncating pointer casts on AArch64. · 037af52c
  Tim Northover authored Oct 31, 2016
  037af52c
- GlobalISel: translate stack protector intrinsics · cdf23f1d
  Tim Northover authored Oct 31, 2016
  cdf23f1d
- [x86][inline-asm][AVX512][llvm][PART-2] · 68a5c536
  Michael Zuckerman authored Oct 31, 2016
  68a5c536
- [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. · 54bfd548
  Artem Tamazov authored Oct 31, 2016
  54bfd548