Commits · e821db39d2255455f0c6fbddbe4529fa5dbec852 · Roger Ferrer / llvm-epi · GitLab

May 26, 2023
- [NFC] refactor code · e821db39
  Luo, Yuanke authored May 26, 2023
  e821db39
- [RISCV] Support '.option arch' directive · 9e8ed340
  luxufan authored May 26, 2023
  9e8ed340
- [RISCV] Don't scalarize vector stores if volatile · 90c4db4a
  Luke Lau authored May 25, 2023
  90c4db4a
- [AMDGPU] Silence gcc warning [NFC] · cafb0991
  Mikael Holmen authored May 26, 2023
  cafb0991
- [AMDGPU] 4-align SGPR triples · e4284a7c
  Jay Foad authored May 25, 2023
  e4284a7c
- [AMDGPU] Add pass to rewrite partially used virtual superregisters after... · 8d0412ce
  Valery Pykhtin authored Dec 09, 2022
  8d0412ce
- [CSKY] Add missing relocation type for FK_Data_4 Fixup · 6922eedd
  Zi Xuan Wu (Zeson) authored May 26, 2023
  
  6922eedd
- [RISCV] Custom lower vector llvm.is.fpclass to vfclass.v · 477d1080
  LiaoChunyu authored May 26, 2023
  477d1080
- [AMDGPUCodegenPrepare] Add NewPM Support · a22ef958
  Anshil Gandhi authored May 24, 2023
  a22ef958
May 25, 2023
- Don't disable loop unroll for vectorized loops on AMDGPU target · bad4de1a
  Alexander Timofeev authored Apr 26, 2023
  bad4de1a
- [NVPTX, CUDA] barrier intrinsics and builtins for sm_90 · 25708b3d
  Artem Belevich authored May 23, 2023
  25708b3d
- [NVPTX] add new sm90-specific intrinsics. · 3d4964f4
  Artem Belevich authored May 19, 2023
  3d4964f4
- [CUDA] bump supported CUDA version to 12.1/11.8 · ffb635cb
  Artem Belevich authored May 23, 2023
  ffb635cb
- [GlobalIsel][X86] fix legalization of G_CTLZ and G_CTPOP · bc713b19
  Thorsten Schütt authored May 17, 2023
  bc713b19
- [RISCV] Fix -Wunused-variable in release builds. NFCI · 236bface
  Alexander Kornienko authored May 25, 2023
  236bface
- [RISCV] Don't reduce vslidedown's VL in rotations · 6fdc77e4
  Luke Lau authored May 25, 2023
  6fdc77e4
- [RISCV][NFC] Simplify decoding code of disassembler · 92723d5a
  Pengcheng Wang authored May 25, 2023
  92723d5a
- [RISCV][CodeGen] Support Zdinx on RV32 codegen · 8b90f8e0
  Shao-Ce SUN authored May 25, 2023
  8b90f8e0
- [MIPS] Check if register is non-null before calling isSuperOrSubRegisterEq (NFCI) · 4374026d
  Sergei Barannikov authored May 24, 2023
  4374026d
- [RISCV] Add a special caes to performVFMADD_VLCombine to support the... · 2f3e1756
  Craig Topper authored May 24, 2023
  2f3e1756
- [RISCV] Remove some unneeded vmacc isel patterns. · 40a274c6
  Craig Topper authored May 24, 2023
  40a274c6
May 24, 2023
- AMDGPU: Replace certain llvm.amdgcn.class uses with llvm.is.fpclass · 9ef1333b
  Matt Arsenault authored Dec 10, 2022
  9ef1333b
- LLVM_FALLTHROUGH => [[fallthrough]]. NFC · 6006d43e
  Craig Topper authored May 24, 2023
  6006d43e
- [RISCV] Use vfslide1down for build_vectors of non-constant floats · 9357712b
  Philip Reames authored May 24, 2023
  9357712b
- [RISCV][InsertVSETVLI] Support constant VLs larger than immediate encoding · 7639a39d
  Philip Reames authored May 24, 2023
  7639a39d
- [PowerPC] Remove asserts from the disassembler. · 11fbd0c6
  Stefan Pintilie authored May 24, 2023
  11fbd0c6
- Revert "[PowerPC] Simplify fp-to-int store optimization" · e7c5ced0
  Vitaly Buka authored May 24, 2023
  e7c5ced0
- [PowerPC] Do not attempt to combine fptoui without FPCVT · de681d53
  Nemanja Ivanovic authored May 24, 2023
  de681d53
- [ARM] Remove unused functions isExpImmValue, isExpImm, and isInvertedExpImm · 94daee2e
  Kazu Hirata authored May 24, 2023
  94daee2e
- [RISCV] Scalarize constant stores of fixed vectors if small enough · a8a36ee5
  Luke Lau authored May 22, 2023
  a8a36ee5
- Revert "[RISCV] Scalarize constant stores of fixed vectors up to 32 bits" · 173855f9
  Luke Lau authored May 24, 2023
  173855f9
- [RISCV] Scalarize constant stores of fixed vectors up to 32 bits · 0ca13f9d
  Luke Lau authored May 22, 2023
  0ca13f9d
- [AMDGPU] Switch to backwards scavenging in non-spill cases · 94e48d43
  Jay Foad authored May 24, 2023
  94e48d43
- [Hexagon] Add more debugging options and dumps to HVC · b9c78deb
  Krzysztof Parzyszek authored May 23, 2023
  
  b9c78deb
- [Hexagon] Remap all instructions generated for aligned address/value in HVC · 538c1416
  Krzysztof Parzyszek authored May 23, 2023
  538c1416
- [AMDGPU] Add attribute to AMDGPU ctor / dtor to indicate single threadedness · 3590945a
  Joseph Huber authored May 22, 2023
  3590945a
- [RISCV] Scalarize small fixed vector copies < XLEN · 28b21c4c
  Luke Lau authored May 22, 2023
  28b21c4c
- AMDGPU: Drop FP_ROUND second value check · 0fe83eb5
  Matt Arsenault authored May 23, 2023
  0fe83eb5
- [AMDGPU] Check if register is non-null before calling isSubRegisterEq (NFCI) · 74204138
  Sergei Barannikov authored May 24, 2023
  74204138
- [BBUtils][NFC] Delete SplitBlockAndInsertIfThen with DT. · 0c316f00
  Joshua Cao authored Apr 27, 2023
  0c316f00