Commits · e855cc6d04ff540b20ff48cd6bfee3fbf85328b9 · Roger Ferrer / llvm-epi · GitLab

Feb 08, 2021
- [AArch64][GlobalISel] Support the 'returned' parameter attribute. · ec41ed5b
  Amara Emerson authored Feb 03, 2021
  ec41ed5b
- [AArch64] Use '//' as comment string for MSVC assembly · 71c29b4c
  Martin Storsjö authored Feb 08, 2021
  71c29b4c
- AArch64: use a constpool for blockaddress(...) on MachO · c93d50dd
  Tim Northover authored Feb 08, 2021
  c93d50dd
- [CodeGen][AArch64] Add TargetInstrInfo hook to modify the TailDuplicateSize default threshold · cd880442
  Nicholas Guy authored Jan 28, 2021
  cd880442
Feb 06, 2021
- [AsmPrinter] __patchable_function_entries: Set SHF_LINK_ORDER for binutils 2.36 and above · 853a2649
  Fangrui Song authored Feb 05, 2021
  853a2649
Feb 05, 2021
- Revert "[Codegen][ReplaceWithVecLib] add pass to replace vector intrinsics... · c981f6f8
  Sanjay Patel authored Feb 05, 2021
  c981f6f8
- [Codegen][ReplaceWithVecLib] add pass to replace vector intrinsics with calls to vector library · 2303e93e
  Lukas Sommer authored Feb 04, 2021
  2303e93e
- [DAGCombiner][SVE] Fix invalid use of getVectorNumElements() in visitSRA. · 1b81117f
  Huihui Zhang authored Feb 05, 2021
  1b81117f
- [ObjC][ARC] Use operand bundle 'clang.arc.rv' instead of explicitly · 4a64d8fe
  Akira Hatanaka authored Jan 25, 2021
  4a64d8fe
- Revert "[ObjC][ARC] Use operand bundle 'clang.arc.rv' instead of explicitly" · 2fbbb18c
  Akira Hatanaka authored Feb 05, 2021
  2fbbb18c
- [ObjC][ARC] Use operand bundle 'clang.arc.rv' instead of explicitly · 3fe3946d
  Akira Hatanaka authored Jan 25, 2021
  3fe3946d
- [AArch64][SVE] Coalesce ptrue instrinsic calls where possible · 3d257fde
  Joe Ellis authored Feb 05, 2021
  3d257fde
Feb 04, 2021
- [AArch64][GlobalISel] Change store value type from p0 -> s64 to import patterns · 56fcd4ea
  Jessica Paquette authored Feb 02, 2021
  56fcd4ea
- [AArch64][GlobalISel] Emit G_ASSERT_ZEXT in assignValueToAddress for ZExt params · a1f6bb20
  Jessica Paquette authored Jan 29, 2021
  a1f6bb20
Feb 03, 2021
- [GlobalISel] Add sext(constant) -> constant artifact combine. · 1a13ee1e
  Amara Emerson authored Jan 29, 2021
  1a13ee1e
- [GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond · 02d4b365
  Jessica Paquette authored Feb 02, 2021
  02d4b365
Feb 02, 2021
- [AArch64] Homogeneous Prolog and Epilog Size Optimization · 4f58b1bd
  Kyungwoo Lee authored Feb 01, 2021
  4f58b1bd
- Revert "[AArch64] Homogeneous Prolog and Epilog Size Optimization" · 8f7f2c42
  Puyan Lotfi authored Feb 02, 2021
  8f7f2c42
- [AArch64] Homogeneous Prolog and Epilog Size Optimization · 0426be3d
  Kyungwoo Lee authored Feb 01, 2021
  0426be3d
Feb 01, 2021
- [AArch64][GlobalISel] Emit G_ASSERT_ZEXT in assignValueToReg · cf2be5e3
  Jessica Paquette authored Jan 27, 2021
  cf2be5e3
- [GlobalISel] Make sure G_ASSERT_ZEXT's src ends up with the same rc as dst · 48096633
  Jessica Paquette authored Jan 29, 2021
  48096633
- GlobalISel: check type size before getZExtValue()ing it. · c2b322fc
  Tim Northover authored Feb 01, 2021
  c2b322fc
Jan 29, 2021
- [ExpandMemCmpPass] Preserve Dominator Tree, if available · ddc4b56e
  Roman Lebedev authored Jan 29, 2021
  ddc4b56e
- [GlobalISel] Remove hint instructions in generic InstructionSelect code. · d6656c3b
  Jessica Paquette authored Jan 28, 2021
  d6656c3b
- [GlobalISel] Implement regbankselect for G_ASSERT_ZEXT · d5736a27
  Jessica Paquette authored Jan 28, 2021
  d5736a27
- [AArch64][GlobalISel] Enable CSE for the prelegalizer combiner. · 12b9b778
  Amara Emerson authored Jan 28, 2021
  12b9b778
- [GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT · f19971d1
  Jessica Paquette authored Jan 27, 2021
  f19971d1
- [AArch64][GlobalISel] Add a combine to fold away truncate in: G_ICMP EQ/NE (G_TRUNC(v), 0) · be62b3ba
  Amara Emerson authored Jan 26, 2021
  be62b3ba
Jan 28, 2021
- Recommit "[GlobalISel] Walk through hints in getDefIgnoringCopies et al" · daffab19
  Jessica Paquette authored Jan 28, 2021
  daffab19
- Revert "[GlobalISel] Walk through hints in getDefIgnoringCopies et al" · dcb5b5f1
  Jessica Paquette authored Jan 28, 2021
  dcb5b5f1
- [GlobalISel] Walk through hints in getDefIgnoringCopies et al · 4580acf6
  Jessica Paquette authored Jan 27, 2021
  4580acf6
- [GlobalISel] Implement widenScalar for carry-in add/sub · f22f4557
  Cassie Jones authored Jan 28, 2021
  f22f4557
- [GlobalISel] Add G_ASSERT_ZEXT · 24261729
  Jessica Paquette authored Jan 27, 2021
  24261729
- [AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer · 42635856
  Bradley Smith authored Jan 07, 2021
  42635856
- [NFC] Move scavenge-lr.mir From AArch64 to Thumb2 test directory. · 9a2bbfae
  Tomas Matheson authored Jan 28, 2021
  
  9a2bbfae
- [ARM][RegisterScavenging] Don't consider LR liveout if it is not reloaded · b9ed8ebe
  Tomas Matheson authored Jan 20, 2021
  b9ed8ebe
Jan 27, 2021
- [AArch64][GlobalISel] Allow vector store legalization into 128-bit-wide types · 3d25fdc5
  Jessica Paquette authored Jan 20, 2021
  3d25fdc5
- [MachineLICM][MachineSink] Move SinkIntoLoop to MachineSink. · 48ecba35
  Sjoerd Meijer authored Jan 08, 2021
  48ecba35
- [Test][AArch64] Use named vregs in overflow legalization tests. NFC · cde1f54f
  Cassie Jones authored Jan 27, 2021
  
  cde1f54f
- [AArch64][GlobalISel] Make G_SADDE and G_SSUBE legal · 40f6599c
  Cassie Jones authored Jan 27, 2021
  40f6599c