Commits · e89b60fcfc7ff776e93a94a54421850cc104a6df · Roger Ferrer / llvm-epi · GitLab

May 18, 2021
- Update MSVC version number in preprocessor check · e89b60fc
  Neal (nealsid) authored May 18, 2021
  e89b60fc
- [RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns · 175bdf12
  Fraser Cormack authored May 17, 2021
  175bdf12
- [VPlan] Add VPUserID to distinguish between recipes and others. · cc1a6361
  Florian Hahn authored May 18, 2021
  cc1a6361
- [RDA] Fix printing of regs / reg units. NFC · b3d38327
  David Green authored May 18, 2021
  b3d38327
- [LV] Return both fixed and scalable Max VF from computeMaxVF. · 81fdc73e
  Sander de Smalen authored May 18, 2021
  81fdc73e
- [Windows SEH]: HARDWARE EXCEPTION HANDLING (MSVC -EHa) - Part 1 · 797ad701
  Ten Tzen authored May 17, 2021
  797ad701
- [Statepoint Lowering] Cleanup: remove unused option statepoint-always-spill-base. · 57c660f3
  Serguei Katkov authored May 18, 2021
  
  57c660f3
- [GVN] Improve analysis for missed optimization remark · ab1f6ffa
  Adam Nemet authored May 17, 2021
  ab1f6ffa
- [PowerPC] only check the load instruction result number 0. · 15d4ed6d
  Chen Zheng authored May 17, 2021
  15d4ed6d
- Revert "[LV] Unconditionally branch from middle to scalar preheader if the... · ed9d7078
  Philip Reames authored May 17, 2021
  ed9d7078
- [Inliner] Copy attributes when deoptimize intrinsic is inlined · 7bed58d2
  Serguei Katkov authored May 17, 2021
  7bed58d2
- [NFC][OpaquePtr] Avoid using PointerType::getElementType() in VectorUtils.cpp · cc64ece7
  Arthur Eubanks authored May 14, 2021
  cc64ece7
- [Matrix] Fold the transpose into the matmul operand used to fetch scalars · fcffd087
  Adam Nemet authored Dec 11, 2020
  fcffd087
- [LV] Unconditionally branch from middle to scalar preheader if the scalar loop must execute (try 3) · 6d3e3ae8
  Philip Reames authored May 17, 2021
  6d3e3ae8
- [AMDGPU] Do not check denorm for LDS FP atomic with unsafe flag · 45764efb
  Stanislav Mekhanoshin authored May 12, 2021
  45764efb
- Revert "[LV] Unconditionally branch from middle to scalar preheader if the... · d16da734
  Philip Reames authored May 17, 2021
  d16da734
- [LV] Unconditionally branch from middle to scalar preheader if the scalar loop must execute · c23ce54b
  Philip Reames authored May 17, 2021
  c23ce54b
May 17, 2021
- [AArch64][SVE] Implement extractelement of i1 vectors. · 3dd49ec1
  Eli Friedman authored Sep 14, 2020
  3dd49ec1
- Do actual DCE in LoopUnroll (try 3) · b6320eeb
  Philip Reames authored May 17, 2021
  b6320eeb
- [WebAssembly] Nullify DBG_VALUE_LISTs in DebugValueManager · 6e1c1dac
  Heejin Ahn authored May 16, 2021
  6e1c1dac
- Revert "X86: support Swift Async context" · 6791a6b3
  Mitch Phillips authored May 17, 2021
  6791a6b3
- [InstCombine] fold fnegs around select · 3cdd05e5
  Sanjay Patel authored May 17, 2021
  3cdd05e5
- [AArch64] Support customizing stack protector guard · 0f417789
  Nick Desaulniers authored May 17, 2021
  0f417789
- [NewPM] Add C bindings for new pass manager · 0c557db6
  Mats Larsen authored May 17, 2021
  0c557db6
- Revert "[NewPM] Add C bindings for new pass manager" · 0b339778
  Nico Weber authored May 17, 2021
  0b339778
- [NewPM] Add C bindings for new pass manager · cd220a06
  Mats Larsen authored May 17, 2021
  cd220a06
- [LoopIdiom] 'logical right-shift until zero' ('count active bits') "on steroids" idiom recognition. · 0633d5ce
  Roman Lebedev authored May 17, 2021
  0633d5ce
- [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX redux.sync instructions · f226e28a
  Steffen Larsen authored May 17, 2021
  f226e28a
- [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX cp.async instructions · 02c24688
  Stuart Adams authored May 17, 2021
  02c24688
- [AMDGPU] Set unused dst_sel to '?' in the encoding · f4c0fdc6
  Stanislav Mekhanoshin authored May 14, 2021
  f4c0fdc6
- [X86] Don't dereference a dyn_cast<> - use a cast<> instead. NFCI. · 41587466
  Simon Pilgrim authored May 17, 2021
  41587466
- [AMDGPU] Tweak VOP3_INTERP16 profile · 472f8567
  Jay Foad authored May 14, 2021
  472f8567
- [AArch64] Lower bitreverse in ISel · 50511df3
  Irina Dobrescu authored May 17, 2021
  50511df3
- [PowerPC] Add patterns for vselect of v1i128 · 511f4ae5
  Nemanja Ivanovic authored May 17, 2021
  511f4ae5
- [PowerPC] Do not emit dssall on AIX · 74ae7781
  Nemanja Ivanovic authored May 17, 2021
  74ae7781
- X86: support Swift Async context · 747e5cfb
  Tim Northover authored Jan 12, 2021
  747e5cfb
- AArch64: mark x22 livein if it's an async context that gets stored. · 769ced3d
  Tim Northover authored May 17, 2021
  769ced3d
- [TargetLowering] prepareUREMEqFold/prepareSREMEqFold - account for non legal shift types · c29522d6
  Simon Pilgrim authored May 17, 2021
  c29522d6
- IR/AArch64/X86: add "swifttailcc" calling convention. · 82a0e808
  Tim Northover authored Nov 19, 2020
  82a0e808
- [AArch64] Lower fpto*i.sat intrinsics. · 900c8989
  Jacob Bramley authored Apr 27, 2021
  900c8989