Commits · e8b303716e76b6ce75673f9e0de3227e5ce3b87f · Roger Ferrer / llvm-epi · GitLab

Feb 10, 2022
- [CSKY] Add missing header include in cpp files because of LLVM headers refactor work · e8b30371
  Zi Xuan Wu authored Feb 10, 2022
  
  e8b30371
- [AMDGPU] Select no-return atomic ops in FLATInstructions.td. · 29bd3fad
  Abinav Puthan Purayil authored Feb 07, 2022
  29bd3fad
- [AMDGPU] Select no-return ds_* atomic ops in tblgen. · f4e8cf25
  Abinav Puthan Purayil authored Dec 27, 2021
  f4e8cf25
- [PowerPC] Add custom lowering for SELECT_CC fp128 using xsmaxcqp · 097a95f2
  Ting Wang authored Feb 09, 2022
  097a95f2
- [X86] Only force FP usage in the presence of pushf/popf on Win64 · f3481f43
  Reid Kleckner authored Feb 09, 2022
  f3481f43
- [RISCV] Add support for matching vwmaccsu/vwmaccus from fixed vectors · c5d3b231
  Chenbing.Zheng authored Feb 10, 2022
  c5d3b231
Feb 09, 2022
- [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to replace sub from constant with neg. · c45c1b13
  Craig Topper authored Feb 09, 2022
  c45c1b13
- [RISCV] Add a really basic cost model for SK_Splice. · 09629215
  Craig Topper authored Feb 09, 2022
  09629215
- [RISCV][VP] Lower VP_FMA to RVV instructions. · 279b3b81
  Craig Topper authored Feb 09, 2022
  279b3b81
- [RISCV] Lower VP_FNEG to RVV instructions · 63e71154
  Craig Topper authored Feb 09, 2022
  63e71154
- [AMDGPU] Remove dead code from shrinkScalarLogicOp · 476bb2d9
  Jay Foad authored Feb 09, 2022
  476bb2d9
- [RISCV] Pre-process integer ISD::SPLAT_VECTOR to RISCISD::VMV_V_X_VL before isel. · e305b1de
  Craig Topper authored Feb 09, 2022
  e305b1de
- [X86] TCRETURNmi fix for 32bit platform · 2fe31516
  Tong Zhang authored Feb 09, 2022
  2fe31516
- Revert "X86: gate all vmovsh instructions on FP16 support." · 8366e182
  Tim Northover authored Feb 09, 2022
  8366e182
- AArch64: do not use xzr for ldxp -> stxp dataflow. · 00e37213
  Tim Northover authored Feb 09, 2022
  00e37213
- X86: gate all vmovsh instructions on FP16 support. · 3fc40b6e
  Tim Northover authored Feb 07, 2022
  3fc40b6e
- [AMDGPU] Remove irrelevant comments on V_BFE_I32 instructions · db28a456
  Jay Foad authored Feb 09, 2022
  db28a456
- [RISCV][NFC] Remove useless code · af2cd945
  Lian Wang authored Feb 09, 2022
  af2cd945
- Cleanup LLVMMC headers · ef736a1c
  serge-sans-paille authored Feb 08, 2022
  ef736a1c
- [X86] Specify Undef for the registers we xor · d295a53a
  Bill Wendling authored Feb 09, 2022
  d295a53a
- [NVPTX] Remove image/sampler special case in call lowering · ff0b3916
  Nikita Popov authored Feb 08, 2022
  ff0b3916
- [RISCV] Select unmasked RVV pseudos in a DAG post-process · 6449bea5
  Fraser Cormack authored Feb 01, 2022
  6449bea5
- [AMDGPU] [NFC] Fix incorrect use of bitwise operator. · c6a6b579
  Sameer Sahasrabuddhe authored Feb 08, 2022
  c6a6b579
- [RISCV][NFC] Refactor RISCVISAInfo. · cfe7f690
  Zakk Chen authored Feb 08, 2022
  cfe7f690
- [RISCV] Add patterns for vector widening floating-point fused multiply-add instructions · 5e71bbfb
  Jianjian GUAN authored Jan 18, 2022
  5e71bbfb
- [X86] Implement -fzero-call-used-regs option · deaf22bc
  Bill Wendling authored Feb 08, 2022
  deaf22bc
- [Hexagon] Fix operation actions for v128f16 · 0792161c
  Krzysztof Parzyszek authored Feb 08, 2022
  0792161c
Feb 08, 2022
- [Hexagon] Fix crash with shuffle_vector of v128f16 · 7403c02f
  Krzysztof Parzyszek authored Feb 04, 2022
  
  7403c02f
- [AMDGPU] Select VGPR versions of MFMA if possible · aeaf85b9
  Stanislav Mekhanoshin authored Jan 12, 2022
  aeaf85b9
- [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs · 56d6ccd4
  Craig Topper authored Feb 08, 2022
  56d6ccd4
- AMDGPU: Use reserved VGPR for AGPR spills to memory · f2c99ea4
  Matt Arsenault authored Feb 04, 2022
  f2c99ea4
- AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908 · 8b2ca766
  Matt Arsenault authored Dec 14, 2021
  8b2ca766
- [AArch64][CodeGen] Always use SVE (when enabled) to lower 64-bit vector multiplies · eabae1b0
  David Sherwood authored Feb 02, 2022
  eabae1b0
- [AMDGPURewriteOutArguments] Don't use pointer element type · 99702734
  Nikita Popov authored Feb 08, 2022
  99702734
- [X86] selectLEAAddr - relax heuristic to only require one operand to be a... · 0b00cd19
  Simon Pilgrim authored Feb 08, 2022
  0b00cd19
- [SDAG] move x86 select-with-identity-constant fold behind a target hook; NFC · a68e0980
  Sanjay Patel authored Feb 08, 2022
  a68e0980
- [AArch64TargetTransformInfo] Avoid pointer element type access · 3196ef8e
  Nikita Popov authored Feb 08, 2022
  3196ef8e
- [VE] v256.32|64 setcc isel and tests · ae1bb44e
  Simon Moll authored Feb 08, 2022
  ae1bb44e
- [ADT] Add APInt/MathExtras isShiftedMask variant returning mask offset/length · fd2bb51f
  Simon Pilgrim authored Feb 08, 2022
  fd2bb51f
- [AArch64] Attempt to emitConjunction from brcond · fdce239a
  David Green authored Feb 08, 2022
  fdce239a