Commits · e93a8137d3046a8b55d23997ffa5f415e8f684d3 · Roger Ferrer / llvm-epi · GitLab

Aug 01, 2023
- [RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2) · e93a8137
  Philip Reames authored Aug 01, 2023
  e93a8137
- [RISCV][test] Add 'atomicrmw xchg a, -1' tests in preparation for D156801 · bc2ea021
  Alex Bradbury authored Aug 01, 2023
  bc2ea021
- [RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM. · 048458f9
  Craig Topper authored Aug 01, 2023
  048458f9
- [RISCV] Generalize 'tryFoldSelectIntOp` to other operations. · 0fb3ebb2
  Mikhail Gudim authored Jul 13, 2023
  0fb3ebb2
- [RISCV][test] Add atomicrmw test cases for suboptimal codegen report in #64090 · fdac86cc
  Alex Bradbury authored Aug 01, 2023
  fdac86cc
- [MISched] Do not erase resource booking history for subunits. · cd921e0f
  Francesco Petrogalli authored Aug 01, 2023
  cd921e0f
- [SPIRV] Add support for SPV_INTEL_optnone · 8f3b87fc
  Paulo Matos authored Jul 26, 2023
  8f3b87fc
- [CSKY] Optimize 'llvm.cttz.i32' and 'llvm.ctlz.i32' · 75c3c6ac
  Ben Shi authored Aug 01, 2023
  75c3c6ac
- [CSKY][NFC][test] Add more tests of CodeGen for intrinsics · f94e9bdc
  Ben Shi authored Jul 28, 2023
  f94e9bdc
- [CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32' · 80cd5059
  Ben Shi authored Jul 06, 2023
  80cd5059
- [RISCV] Use the first element of source as the start value of reduction. · 4c8cf920
  Yeting Kuo authored Jul 21, 2023
  4c8cf920
- [RISCV] Expand load extension / truncate store for bf16 · 934b4905
  Jun Sha (Joshua) authored Aug 01, 2023
  934b4905
- [BPF] Match CHECK w/ LLVM_ENABLE_ASSERTIONS=OFF (D156136) · 59afd298
  Tamir Duberstein authored Aug 01, 2023
  
  59afd298
- Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting" · 4d42e8b5
  Matt Arsenault authored Jul 28, 2023
  4d42e8b5
- Revert "Reland "[LoongArch] Support -march=native and -mtune="" · 42c9354a
  Steven Wu authored Jul 31, 2023
  42c9354a
- AMDGPU: Move placement of RemoveIncompatibleFunctions · 5b5bd81b
  Matt Arsenault authored Jul 01, 2023
  5b5bd81b
- AMDGPU: Directly emit fabs intrinsic instead of new libcall · db4d6ef9
  Matt Arsenault authored Jul 31, 2023
  
  db4d6ef9
- AMDGPU: Remove weird usage of implicit operand on COPY · 02a0b113
  Matt Arsenault authored Jul 25, 2023
  02a0b113
- AMDGPU/GlobalISel: Use SGPR results for G_AMDGPU_WAVE_ADDRESS · 0aa439d5
  Matt Arsenault authored Jul 30, 2023
  
  0aa439d5
Jul 31, 2023
- [BPF] Clean up SelLowering · d542a56c
  Tamir Duberstein authored Jul 31, 2023
  d542a56c
- [AArch64] Add some basic handling for bf16 constants. · 778fa4ed
  David Green authored Jul 31, 2023
  778fa4ed
- [X86] Allow pre-SSE41 targets to extract multiple v16i8 elements coming from... · 071671e1
  Simon Pilgrim authored Jul 31, 2023
  071671e1
- AMDGPU: Partially respect nobuiltin in libcall simplifier · 8a677a7f
  Matt Arsenault authored Jul 30, 2023
  8a677a7f
- [DAG] getNode() - fold (zext (trunc (assertzext x))) -> (assertzext x) · 076bee10
  Simon Pilgrim authored Jul 30, 2023
  076bee10
- Retain all jump table range checks when using BTI. · 60b98363
  Simon Tatham authored Jul 31, 2023
  60b98363
- [llc] Add the command line option `-sched-model-force-enable-intervals`. · c4b21d57
  Francesco Petrogalli authored Jul 31, 2023
  c4b21d57
- Reapply [IR] Mark and/or constant expressions as undesirable · 063b37e7
  Nikita Popov authored Jul 20, 2023
  063b37e7
- [GlobalISel] convergent intrinsics · d9847cde
  Sameer Sahasrabuddhe authored Jul 31, 2023
  d9847cde
- [AArch64][GlobalISel] G_FMINNUM and G_FMAXNUM vector lowering · e8e49a35
  David Green authored Jul 31, 2023
  e8e49a35
- [RISCV] Remove unused CHECK prefix from test. NFC · eff53ce8
  Craig Topper authored Jul 30, 2023
  
  eff53ce8
- [CSKY] Add more IR patterns to select FNMUL · 14e0a67a
  Ben Shi authored Jul 13, 2023
  14e0a67a
- [RISCV] Use x0 in vsetvli when avl is equal to vlmax. · b7408ebb
  Jianjian GUAN authored Jul 27, 2023
  b7408ebb
Jul 30, 2023
- [AArch64] Add a fminnum/fmaxnum test. NFC · cf39dea5
  David Green authored Jul 30, 2023
  cf39dea5
- [AArch64] Regenerate arm64-vabs.ll, arm64-subvector-extend.ll and some mir tests. NFC · 76f0d186
  David Green authored Jul 30, 2023
  
  76f0d186
- [Hexagon] Add machine verification to some tests · 58642565
  Jay Foad authored Jul 30, 2023
  58642565
Jul 29, 2023
- Revert "[MachineScheduler] Track physical register dependencies per-regunit" · e2e3f068
  Jay Foad authored Jul 29, 2023
  e2e3f068
- [MachineScheduler] Track physical register dependencies per-regunit · 1a54671d
  Jay Foad authored Jul 28, 2023
  1a54671d
- [MachineScheduler] Test case for physical register dependencies · 5a64c89c
  Jay Foad authored Jul 28, 2023
  5a64c89c
- [AArch64] Refactor checks in sign-return-address.ll test · 4210204f
  Anatoly Trosinenko authored Jul 29, 2023
  4210204f
- [XCOFF] Do not put MergeableCStrings in their own section · 9d4e8c09
  Wael Yehia authored Jul 26, 2023
  9d4e8c09