Commits · ea4f653d18e74439f0abefe5861d05fea9ddf5d0 · Roger Ferrer / llvm-epi · GitLab

Nov 06, 2015
- [mips][ias] Range check uimm2 operands and fix a bug this revealed. · ea4f653d
  Daniel Sanders authored Nov 06, 2015
  ea4f653d
- [mips][ias] Range check uimmz operands. · 52da7af4
  Daniel Sanders authored Nov 06, 2015
  52da7af4
- [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes. · b04672ca
  Vasileios Kalintiris authored Nov 06, 2015
  b04672ca
- AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL · 1e1b05db
  Tom Stellard authored Nov 06, 2015
  1e1b05db
- [WinEH] Split EH_RESTORE out of CATCHRET for 32-bit EH · 51460c13
  Reid Kleckner authored Nov 06, 2015
  51460c13
Nov 05, 2015
- Remove windows line endings introduced by r252177. NFC. · 775aaeb7
  Tim Northover authored Nov 05, 2015
  775aaeb7
- [WinEH] Fix funclet prologues with stack realignment · 6ddae310
  Reid Kleckner authored Nov 05, 2015
  6ddae310
- [WebAssembly] Fix copypasta. · b9ce5a8b
  Dan Gohman authored Nov 05, 2015
  b9ce5a8b
- [WebAssembly] Rename Immediate instructions to Const. · da7f428a
  Dan Gohman authored Nov 05, 2015
  da7f428a
- [WebAssembly] Add AsmString strings for most instructions. · af29bd4f
  Dan Gohman authored Nov 05, 2015
  af29bd4f
- [WebAssembly] Update wasm builtin functions to match spec changes. · d7ffb919
  Dan Gohman authored Nov 05, 2015
  d7ffb919
- replace MachineCombinerPattern namespace and enum with enum class; NFCI · 387e66e7
  Sanjay Patel authored Nov 05, 2015
  387e66e7
- [WebAssembly] Add WebAssemblyMCInstLower.cpp. · e9361d58
  Dan Gohman authored Nov 05, 2015
  e9361d58
- [DebugInfo] Fix ARM/AArch64 prologue_end position. Related to D11268. · 057c5a6b
  Oleg Ranevskyy authored Nov 05, 2015
  057c5a6b
- Add cfi instr for CFA calculation when movpc is expanded to call and pop · 99fba3c1
  Petar Jovanovic authored Nov 05, 2015
  99fba3c1
- [WebAssembly] Rename ior operator to or to match the spec · 8a76b04a
  Derek Schuff authored Nov 05, 2015
  8a76b04a
- [ARM] Compute known bits for ARMISD::CMOV · bef6e431
  James Molloy authored Nov 05, 2015
  bef6e431
- revert rev. 252153 due to build failure on ubuntu · f99c054e
  Asaf Badouh authored Nov 05, 2015
  f99c054e
- [X86][AVX512] add comi with Sae · 7fdabf0a
  Asaf Badouh authored Nov 05, 2015
  7fdabf0a
- [X86][AVX512] small bugfix in VPBROADCASTM · a8209d92
  Asaf Badouh authored Nov 05, 2015
  a8209d92
- AMDGPU: Also track whether SGPRs were spilled · 5b22dfa6
  Matt Arsenault authored Nov 05, 2015
  5b22dfa6
- AMDGPU: Print number user SGPRs · d41c0dbf
  Matt Arsenault authored Nov 05, 2015
  d41c0dbf
- AMDGPU: Disallow s[102:103] on VI in assembler · 68802d31
  Matt Arsenault authored Nov 05, 2015
  68802d31
- AMDGPU: Fix assert when legalizing atomic operands · a40450cb
  Matt Arsenault authored Nov 05, 2015
  a40450cb
- AMDGPU: Make addr64 atomic operand order consistent · bed42a73
  Matt Arsenault authored Nov 05, 2015
  bed42a73
- [WinEH] Fix establisher param reg in CLR funclets · 6afccf61
  Joseph Tremoulet authored Nov 05, 2015
  6afccf61
- Go back to producing relocations for out of range symbols. · e61a9023
  Rafael Espindola authored Nov 05, 2015
  e61a9023
- AMDGPU: Fix typo · 6c2e200d
  Matt Arsenault authored Nov 05, 2015
  6c2e200d
- Slightly saner handling of thumb branches. · 49b85489
  Rafael Espindola authored Nov 04, 2015
  49b85489
Nov 04, 2015
- [x86] Teach the shrink-wrapping hooks to do the proper thing with Win64. · 421723cd
  Quentin Colombet authored Nov 04, 2015
  421723cd
- Warning fix. · f669d381
  Simon Pilgrim authored Nov 04, 2015
  f669d381
- [X86][SSE] Add general memory folding for (V)INSERTPS instruction · 7e6606f4
  Simon Pilgrim authored Nov 04, 2015
  7e6606f4
- [IR] Add bounds checking to paramHasAttr · b11b440f
  Sanjoy Das authored Nov 04, 2015
  b11b440f
- Created new X86 FMA3 opcodes (FMA*_Int) that are used now for lowering of scalar FMA intrinsics. · e41a8c41
  Andrew Kaylor authored Nov 04, 2015
  e41a8c41
- [ARM] Combine CMOV into BFI where possible · e7d679cf
  James Molloy authored Nov 04, 2015
  e7d679cf
- [ELF] elfiamcu triple should imply e_machine == EM_IAMCU · a3b79dd7
  Michael Kuperstein authored Nov 04, 2015
  a3b79dd7
- [X86] DAGCombine should not introduce FILD in soft-float mode · b34de722
  Michael Kuperstein authored Nov 04, 2015
  b34de722
- CodeGen, Target: Move Mach-O-specific symbol name logic to Mach-O lowering. · 94d77869
  Peter Collingbourne authored Nov 03, 2015
  94d77869
Nov 03, 2015
- AMDGPU: Make flat_scratch name consistent · aac9b493
  Matt Arsenault authored Nov 03, 2015
  aac9b493
- AMDGPU: Fix asserts on invalid register ranges · 967c2f5d
  Matt Arsenault authored Nov 03, 2015
  967c2f5d