Commits · eb4d5a9b0b30d6754e5308dc3650ffe609cc1d07 · Roger Ferrer / llvm-epi · GitLab

Apr 13, 2016
- [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status · eb4d5a9b
  Artem Tamazov authored Apr 13, 2016
  eb4d5a9b
- [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly · 2f6845ba
  Zoran Jovanovic authored Apr 13, 2016
  2f6845ba
- [mips] Sign-extend i32 values truncated from previously zero-extended i32 values. · 3751d411
  Vasileios Kalintiris authored Apr 13, 2016
  3751d411
- [X86][SSE] Regenerated vector integer absolute tests · cc901b57
  Simon Pilgrim authored Apr 13, 2016
  cc901b57
- Added missing autogeneration note · b6ef8b73
  Simon Pilgrim authored Apr 13, 2016
  b6ef8b73
- [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD,... · 58d6a959
  Zlatko Buljan authored Apr 13, 2016
  58d6a959
- [mips][microMIPS] Fix for "Cannot copy registers" assertion · 11dd31df
  Hrvoje Varga authored Apr 13, 2016
  11dd31df
- Recommit r265547, and r265610,r265639,r265657 on top of it, plus · 9a16d655
  Wei Mi authored Apr 13, 2016
  9a16d655
- AMDGPU: Add test for m0 initialization in basic loop · 887d4767
  Matt Arsenault authored Apr 13, 2016
  887d4767
- CodeGen: Clear the MFI's save and restore point after PrologEpilogInserter · 263f314b
  Justin Bogner authored Apr 12, 2016
  263f314b
Apr 12, 2016
- AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics · df77c9ad
  Nicolai Haehnle authored Apr 12, 2016
  df77c9ad
- [WebAssembly] Fix debug info in reg-stackify.ll test · b861ec87
  Derek Schuff authored Apr 12, 2016
  b861ec87
- AMDGPU/SI: Insert wait states required after v_readfirstlane on SI · ab1d3a9d
  Tom Stellard authored Apr 12, 2016
  ab1d3a9d
- AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32 · 3b08238f
  Matt Arsenault authored Apr 12, 2016
  3b08238f
- AMDGPU/SI: Fix a mis-compilation of multi-level breaks · 279970c0
  Nicolai Haehnle authored Apr 12, 2016
  279970c0
- Support arbitrary addrspace pointers in masked load/store intrinsics · dbe0bc8d
  Artur Pilipenko authored Apr 12, 2016
  dbe0bc8d
- [ScheduleDAGInstrs] Handle instructions with multiple MMOs · c0739d83
  Geoff Berry authored Apr 12, 2016
  c0739d83
- Test commit, NFC. · b9049084
  Than McIntosh authored Apr 12, 2016
  b9049084
- AMDGPU: Implement i64 global atomics · 64fa2f45
  Matt Arsenault authored Apr 12, 2016
  64fa2f45
- AMDGPU: Add atomic_inc + atomic_dec intrinsics · a9dbdcae
  Matt Arsenault authored Apr 12, 2016
  a9dbdcae
- AMDGPU: Add volatile to test loads and stores · 44e5483a
  Matt Arsenault authored Apr 12, 2016
  44e5483a
- [X86] Regenerated avx512 calling convention test checks · edf100e4
  Simon Pilgrim authored Apr 12, 2016
  edf100e4
- Revert "[mips] MIPSR6 Compact branch aliases" · ee1590f5
  Simon Dardis authored Apr 12, 2016
  ee1590f5
- [mips] MIPSR6 Compact branch aliases · 703c864f
  Simon Dardis authored Apr 12, 2016
  703c864f
- [PPC64] Mark CR0 Live if PPCInstrInfo::optimizeCompareInstr Creates a Use of CR0 · 94f58e79
  Chuang-Yu Cheng authored Apr 12, 2016
  94f58e79
- [PPC64] Use mfocrf in prologue when we only need to save 1 nonvolatile CR field · 6efde2fb
  Chuang-Yu Cheng authored Apr 12, 2016
  6efde2fb
- [AArch64] Add test cases for the repairing of physical registers. · 5933eb84
  Quentin Colombet authored Apr 12, 2016
  5933eb84
- [AArch64] Add a test case for the propagation of register banks through · f43f882f
  Quentin Colombet authored Apr 12, 2016
  f43f882f
- [AArch64] Add a test case for the repairing of definitions. · 99d19d89
  Quentin Colombet authored Apr 12, 2016
  99d19d89
- [AArch64] Test that RegBankSelect inserts the proper copies to fix the · d52f4128
  Quentin Colombet authored Apr 12, 2016
  d52f4128
- [safestack] Add canary to unsafe stack frames · f17120a8
  Evgeniy Stepanov authored Apr 11, 2016
  f17120a8
- ARM: use r7 as the frame-pointer on all MachO targets. · a6dea06f
  Tim Northover authored Apr 11, 2016
  a6dea06f
Apr 11, 2016
- swifterror: fix up a testing case. · 2aa7f232
  Manman Ren authored Apr 11, 2016
  2aa7f232
- [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))... · 82e54871
  Simon Pilgrim authored Apr 11, 2016
  82e54871
- Swift Calling Convention: swifterror target support. · 5751814e
  Manman Ren authored Apr 11, 2016
  5751814e
- Revert "AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermute" · 0ffdf65e
  Tom Stellard authored Apr 11, 2016
  0ffdf65e
- More upgrading of old- and very-old-style debug info in testcases. · b01a4d48
  Adrian Prantl authored Apr 11, 2016
  b01a4d48
- [mips] Make Static a default relocation model for MIPS codegen · e578e970
  Petar Jovanovic authored Apr 11, 2016
  e578e970
- [SystemZ] Support conditional indirect sibling calls via BCR · 848a513d
  Ulrich Weigand authored Apr 11, 2016
  848a513d
- [X86] Added extra widening tests for and/xor/or bit operations · ac0cac3b
  Simon Pilgrim authored Apr 11, 2016
  ac0cac3b