Commits · eb764a7f38df48a818cb10777f59fdae13a0c661 · Roger Ferrer / llvm-epi · GitLab

Jun 01, 2023
- [AArch64] Increase the cost of i1 inserts / extracts · eb764a7f
  David Green authored Jun 01, 2023
  eb764a7f
- [X86] Align stack to 16-bytes on 32-bit with X86_INTR call convention · b7e110fc
  Antonio Abbatangelo authored Jun 01, 2023
  b7e110fc
- [AArch64] Adjust costs of i1 and/or/xor reductions · e79fac29
  David Green authored Jun 01, 2023
  e79fac29
- [X86][BF16] Fix 2 crashes with vector broadcast · 801dd887
  Phoebe Wang authored Jun 01, 2023
  801dd887
- [RISCV][NFC] Add isF argument to SchedSEWSet · 78a22401
  Pengcheng Wang authored Jun 01, 2023
  78a22401
May 31, 2023
- [X86] Use "l" prefix for data sections under medium/large code model · 43249378
  Arthur Eubanks authored May 10, 2023
  43249378
- [RISCV] Change LdPat and StPat from multiclass to class. NFC · cf229033
  Craig Topper authored May 31, 2023
  cf229033
- [RISCV] Use class and inheritance instead of multiclass for some vector isel patterns. NFC · 6cc17b28
  Craig Topper authored May 31, 2023
  
  6cc17b28
- [RISCV] Lower extern_weak symbols using the GOT for the medany model · a178ba9f
  Jessica Clarke authored May 31, 2023
  a178ba9f
- [RISCV] Add new lga pseudoinstruction · 9b55e5d4
  Jessica Clarke authored May 31, 2023
  9b55e5d4
- [RISCV][InsertVSETVLI] Relax tail policy more often for vmv.s.x · f3b39cea
  Luke Lau authored May 31, 2023
  f3b39cea
- [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block · badf11de
  Luke Lau authored May 31, 2023
  badf11de
- [RISCV][InsertVSETVLI] Move vmv.s.x SEW check into getDemandedBits. NFC · 257cc049
  Luke Lau authored May 26, 2023
  257cc049
- Revert "[RISCV] Add Zvfhmin extension for clang." · a5e5eea2
  Craig Topper authored May 31, 2023
  a5e5eea2
- Revert "[RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block" · 319adf5d
  Luke Lau authored May 31, 2023
  319adf5d
- [RISCV][InsertVSETVLI] Avoid vmv.s.x SEW toggle if at start of block · 0ba41dd3
  Luke Lau authored May 31, 2023
  0ba41dd3
- [RISCV] Fix an unused variable warning · 6eef8d9b
  Kazu Hirata authored May 31, 2023
  6eef8d9b
- [X86] X86FixupVectorConstantsPass - use VBROADCASTSS/VBROADCASTSD for integer... · d6a36619
  Simon Pilgrim authored May 31, 2023
  d6a36619
- [RISCV] Use v(f)slide1down for shuffle+insert idiom · e6931813
  Philip Reames authored May 31, 2023
  e6931813
- [GlobalIsel][X86] Legalize G_CTLZ and G_CTPOP for 32-bit · dd2fea9c
  Thorsten Schütt authored May 25, 2023
  dd2fea9c
- [X86] printConstant - fix asm comment issue when broadcasting from a wider constant pool entry · f1a42300
  Simon Pilgrim authored May 31, 2023
  f1a42300
- [X86] getTargetConstantBitsFromNode - ensure we truncate broadcasts from wider constants. · 65dce67f
  Simon Pilgrim authored May 31, 2023
  65dce67f
- [RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT · 548fa1d3
  LiaoChunyu authored May 31, 2023
  548fa1d3
- [RISCV] Add Zvfhmin extension for clang. · 35a00792
  Jianjian GUAN authored May 25, 2023
  35a00792
- [RISCV] Merge emitDirectiveOptionArchPlus and emitDirectiveOptionArchMinus... · ac1df223
  Craig Topper authored May 30, 2023
  ac1df223
- [RISCV] Strengthen some SDTypeProfiles to reduce isel table size. · 0a4ba485
  Craig Topper authored May 30, 2023
  
  0a4ba485
- [RISCV] Fix selection for some unmasked vp SDNode. · 62307f6d
  Jianjian GUAN authored May 30, 2023
  62307f6d
- [RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply. · 45416335
  Craig Topper authored May 30, 2023
  
  45416335
May 30, 2023
- [AMDGPU][IGLP] Parameterize the SchedGroup processing / linking order in Solver · 1721e72d
  Jeffrey Byrnes authored Apr 27, 2023
  1721e72d
- [RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace isel patterns with a DAG combine. · 463f50b4
  Craig Topper authored May 30, 2023
  463f50b4
- [RISCV][GlobalISel] Add lowerFormalArguments for calling convention · af8e3861
  Nitin John Raj authored May 30, 2023
  af8e3861
- [CodeGen] Refactor IR generation functions to use IRBuilder in ComplexDeinterleaving pass · 40a81d31
  Igor Kirillov authored Apr 19, 2023
  40a81d31
- [RISCV] Use v(f)slide1up for shuffle+insert idiom · 544a240f
  Philip Reames authored May 30, 2023
  544a240f
- [RISCV][NFC] Make Reduction scheduler resources SEW aware · d70573b1
  Michael Maitland authored May 25, 2023
  d70573b1
- [X86] Fix SunnyCove ROB/MicroOpBufferSize · 9d6f2b19
  Simon Pilgrim authored May 30, 2023
  9d6f2b19
- [X86] lowerBuildVectorAsBroadcast - remove repeated hasAVX() check. NFC. · f81f32ad
  Simon Pilgrim authored May 30, 2023
  f81f32ad
- [X86] X86FixupVectorConstantsPass - attempt to replace full width integer... · ab4b9248
  Simon Pilgrim authored May 29, 2023
  ab4b9248
- [X86] getTargetConstantBitsFromNode - support extracting fp data from ConstantDataSequential · 95661b9c
  Simon Pilgrim authored May 30, 2023
  95661b9c
- [RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all <XLEN floats on soft ABIs · c4efcd69
  Alex Bradbury authored May 30, 2023
  c4efcd69
- [ms-inline asm] Add error check for `getAsInteger` · 8f386ff6
  Phoebe Wang authored May 30, 2023
  8f386ff6