Commits · ed402291ae1b5fa5c057b8ffeae0e1d22b72ad75 · Roger Ferrer / llvm-epi · GitLab

Feb 07, 2022
- [InstCombine] generalize 2 LSB of demanded bits for X*X · 897d92fa
  Sanjay Patel authored Feb 07, 2022
  897d92fa
- [ARM] Undeprecate complex IT blocks · 3d766214
  Mark Murray authored Jan 24, 2022
  3d766214
- [x86] avoid false dependency stall on 'sbb' with same source reg · 40a50f87
  Sanjay Patel authored Feb 07, 2022
  40a50f87
- [InstCombine] add test for demanded 2 low bits of X*X; NFC · 3c33b20e
  Sanjay Patel authored Feb 07, 2022
  
  3c33b20e
- AMDGPU: Fix clobbering SCC when expanding large offset spill pseudos · 31973062
  Matt Arsenault authored Nov 01, 2021
  31973062
- [AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP · be826cf4
  David Truby authored Jan 27, 2022
  be826cf4
- [InstCombine] SimplifyDemandedBits - mul(x,x) is odd iff x is odd · 79b3fe80
  Sanjay Patel authored Feb 05, 2022
  79b3fe80
- [test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC · acdc419c
  Bjorn Pettersson authored Feb 04, 2022
  acdc419c
- [test] Use -passes=instsimplify instead of -instsimplify in a number of tests. NFC · b280ee1d
  Bjorn Pettersson authored Feb 04, 2022
  b280ee1d
- [LV] Remove `LoopVectorizationCostModel::useEmulatedMaskMemRefHack()` · 77a0da92
  Roman Lebedev authored Feb 07, 2022
  77a0da92
- [X86][SSE] Add some initial PAVGB/PAVGW tests · 2e0409a5
  Simon Pilgrim authored Feb 07, 2022
  2e0409a5
- [LV] Modernize some runtime check tests a bit. · ef4df279
  Florian Hahn authored Feb 07, 2022
  ef4df279
- [DebugInfo][test] XFAIL DebugInfo/Generic/missing-abstract-variable.ll on SPARC · 9576698a
  Rainer Orth authored Feb 07, 2022
  9576698a
- [Bitcode] Replace assertion with check · f4fca0fb
  Nikita Popov authored Feb 07, 2022
  
  f4fca0fb
- [Bitcode] Add missing test file · 747fab90
  Nikita Popov authored Feb 07, 2022
  747fab90
- [Bitcode] Handle invalid data layout gracefully · fdf8cb97
  Nikita Popov authored Feb 07, 2022
  
  fdf8cb97
- [Bitcode] Guard against out of bounds value reference · 0c553bff
  Nikita Popov authored Feb 07, 2022
  0c553bff
- [Bitstream] Check that there is enough space for blob · ec18030f
  Nikita Popov authored Feb 07, 2022
  ec18030f
- [Bitcode] Don't assert on invalid attribute group record · 89017772
  Nikita Popov authored Feb 07, 2022
  89017772
- [Bitstream] Reject implausibly large reservations · 3c86642e
  Nikita Popov authored Feb 07, 2022
  3c86642e
- [CSKY] Add inline asm constraints and related codegen support · a190fcdf
  Zi Xuan Wu authored Feb 07, 2022
  a190fcdf
- [X86] Add fp80 copysign test coverage · 289b8e0d
  Simon Pilgrim authored Feb 07, 2022
  289b8e0d
- [Bitcode] Handle invalid abbrev number error more gracefully · 8a718541
  Nikita Popov authored Feb 07, 2022
  8a718541
- [X86] Add test cases for fmul/fdiv with select. · 24562bab
  Luo, Yuanke authored Feb 07, 2022
  
  24562bab
- [JITLink] Fix the incorrect relocation behavior for R_RISCV_BRANCH · 9920943e
  luxufan authored Jan 26, 2022
  9920943e
- [NFC] Precommit test case for PR53357 · 1391f91b
  Chuanqi Xu authored Feb 07, 2022
  
  1391f91b
- [DAGCombiner][AArch64] Enhance to support for scalar CSINC · b3b129f1
  zhongyunde 00443407 authored Jan 10, 2022
  b3b129f1
- [X86] Add pre-commit test for bit test optimization. NFC · 8bb32e5c
  Phoebe Wang authored Feb 07, 2022
  
  8bb32e5c
Feb 06, 2022
- [LoopInterchange] Support loop interchange with floating point reductions · 1ef04326
  Congzhe Cao authored Feb 06, 2022
  1ef04326
- [InstCombine] Add mul(x,x) tests showing miscompile · b9328775
  Simon Pilgrim authored Feb 06, 2022
  b9328775
- [DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb. · c35ccd2a
  Craig Topper authored Feb 06, 2022
  c35ccd2a
- [DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur · cecf11c3
  Bjorn Pettersson authored Feb 02, 2022
  cecf11c3
- Pre-commit test cases for DAG combine folds of SSHLSAT/USHLSAT -> SHL · 0f685976
  Bjorn Pettersson authored Feb 02, 2022
  0f685976
- [ARM] Mark i64 and f64 shuffles as Custom for MVE · b7d3a2b6
  David Green authored Feb 06, 2022
  b7d3a2b6
- [ARM] Add extra vabd, vhadd and vmulh tests. NFC · 3dff4f5c
  David Green authored Feb 06, 2022
  3dff4f5c
- [X86] Fold ZERO_EXTEND_VECTOR_INREG(BUILD_VECTOR(X,Y,?,?)) -> BUILD_VECTOR(X,0,Y,0) · 74b98ab1
  Simon Pilgrim authored Feb 06, 2022
  74b98ab1
- [RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb. · f3a725af
  Craig Topper authored Feb 05, 2022
  f3a725af
- AMDGPU: Don't clobber source register for V_SET_INACTIVE_* · 0719c437
  Ruiling Song authored Jan 17, 2022
  0719c437
- AMDGPU: add test to show wwm register overwrite issue · 2f4d44bc
  Ruiling Song authored Jan 18, 2022
  2f4d44bc
Feb 05, 2022
- Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." · c1cef111
  Craig Topper authored Feb 05, 2022
  c1cef111