Commits · ed721e32cdc877a0f37c5cb48c735e9890e68331 · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2017
- [AArch64] Adjust the cost model for Exynos M1 and M2 · ed721e32
  Evandro Menezes authored Nov 22, 2017
  ed721e32
Nov 21, 2017
- [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. · fe97d736
  Chad Rosier authored Nov 21, 2017
  fe97d736
Nov 20, 2017
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 46f672b7
  Evandro Menezes authored Nov 20, 2017
  46f672b7
- [AArch64][TableGen] Skip tied result operands for InstAlias · 0c5a29b6
  Sander de Smalen authored Nov 20, 2017
  0c5a29b6
Nov 18, 2017
- [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR · c0d34d38
  Quentin Colombet authored Nov 18, 2017
  c0d34d38
- [AArch64] Map G_STORE on FPR when the source comes from a FPR copy · 63816c09
  Quentin Colombet authored Nov 18, 2017
  63816c09
- [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies · 91801f68
  Quentin Colombet authored Nov 18, 2017
  91801f68
Nov 17, 2017
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 4b964f2b
  Evandro Menezes authored Nov 17, 2017
  4b964f2b
- Fix a bunch more layering of CodeGen headers that are in Target · b3bde2ea
  David Blaikie authored Nov 17, 2017
  b3bde2ea
Nov 16, 2017
- [globalisel][tablegen] Generate rule coverage and use it to identify untested rules · f76f3154
  Daniel Sanders authored Nov 16, 2017
  f76f3154
- Add backend name to Target to enable runtime info to be fed back into TableGen · 725584e2
  Daniel Sanders authored Nov 15, 2017
  725584e2
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 82665b1e
  Evandro Menezes authored Nov 15, 2017
  82665b1e
Nov 15, 2017
- [AArch64] Refactor the loads and stores optimizer · 5ba804bc
  Evandro Menezes authored Nov 15, 2017
  5ba804bc
- [AArch64] Adjust the cost model for Exynos M1 and M2 · cbf70486
  Evandro Menezes authored Nov 15, 2017
  cbf70486
- [AArch64][SVE] Asm: Report SVE parsing diagnostics only once · 8e607346
  Sander de Smalen authored Nov 15, 2017
  8e607346
Nov 14, 2017
- [AArch64] Adjust the cost model for Exynos M1 and M2 · 1c945386
  Evandro Menezes authored Nov 14, 2017
  1c945386
- [ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting TLS. NFC. · 4629f523
  Martin Storsjö authored Nov 14, 2017
  4629f523
Nov 13, 2017
- Test commit · 070a7ff1
  Sander de Smalen authored Nov 13, 2017
  070a7ff1
Nov 08, 2017
- Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering · 3f833edc
  David Blaikie authored Nov 08, 2017
  3f833edc
Nov 07, 2017
- [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ · b9368108
  Florian Hahn authored Nov 07, 2017
  b9368108
- [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support · 91f11e5a
  Florian Hahn authored Nov 07, 2017
  91f11e5a
- [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. · d825bbdc
  Florian Hahn authored Nov 07, 2017
  d825bbdc
- [AArch64][SVE] Asm: Replace 'IsVector' by 'RegKind' in AArch64AsmParser (NFC) · c4422247
  Florian Hahn authored Nov 07, 2017
  c4422247
- [GlobalISel] Enable legalizing non-power-of-2 sized types. · af9814a1
  Kristof Beyls authored Nov 07, 2017
  af9814a1
Nov 03, 2017
- Move TargetFrameLowering.h to CodeGen where it's implemented · 1be62f03
  David Blaikie authored Nov 03, 2017
  1be62f03
- [AArch64] Fix the number of iterations for the Newton series · 9dcf0999
  Evandro Menezes authored Nov 03, 2017
  9dcf0999
- [AArch64] Use dwarf exception handling on MinGW · 9befcd7d
  Martin Storsjö authored Nov 03, 2017
  9befcd7d
- [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. · b6afac1f
  Quentin Colombet authored Nov 02, 2017
  b6afac1f
- [AArch64][RegisterBankInfo] Add FPR16 support in value mapping. · 619d6498
  Quentin Colombet authored Nov 02, 2017
  619d6498
Oct 30, 2017
- [AArch64]: range loopify frame-lowering · d13d419d
  Javed Absar authored Oct 30, 2017
  d13d419d
Oct 28, 2017
- [SimplifyCFG] use pass options and remove the latesimplifycfg pass · b0491731
  Sanjay Patel authored Oct 28, 2017
  b0491731
Oct 27, 2017
- InstructionSelectorImpl.h: Modularize/remove ODR violations by using a static... · 62651300
  David Blaikie authored Oct 26, 2017
  62651300
Oct 26, 2017
- Clear LastMappingSymbols and LastEMS(Info) when resetting the ARM(AArch64)ELFStreamer · 221dae31
  Yichao Yu authored Oct 26, 2017
  221dae31
- [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell... · 0551556e
  Craig Topper authored Oct 26, 2017
  0551556e
- [AsmParser][TableGen] Make the generated mnemonic spell checker function a... · 2a06028c
  Craig Topper authored Oct 26, 2017
  2a06028c
Oct 25, 2017
- [AArch64] Add support for dllimport of values and functions · 373c8efa
  Martin Storsjö authored Oct 25, 2017
  373c8efa
Oct 23, 2017
- [globalisel][tablegen] Import stores and allow GISel to automatically... · d66e0901
  Daniel Sanders authored Oct 23, 2017
  d66e0901
Oct 20, 2017
- [globalisel][tablegen] Fix small spelling nits. NFC · 1e4569fd
  Daniel Sanders authored Oct 20, 2017
  1e4569fd
Oct 18, 2017
- [aarch64][globalisel] Register banks and classes should have distinct names. · 30247fd1
  Daniel Sanders authored Oct 18, 2017
  30247fd1
Oct 17, 2017
- AArch64: Enable AES instruction fusion on Cyclone. · a2f96b5b
  Matthias Braun authored Oct 17, 2017
  a2f96b5b