Commits · ed90cf1873aa696f7c99ea2eafc540206c2391e1 · Roger Ferrer / llvm-epi · GitLab

May 17, 2023
- [RISCV][MC] Refine MCInstrAnalysis based on registers used · ed90cf18
  Job Noorman authored May 17, 2023
  ed90cf18
- [RISCV] Allow LI with symbol difference as constant · d045f1d3
  Job Noorman authored May 17, 2023
  d045f1d3
- [AArch64][NFC] Refactor the tail-folding option · 7beb2ca8
  David Sherwood authored Apr 20, 2023
  7beb2ca8
- [AMDGPU] Add missing whitespace in SIInstrInfo header (NFC) · 0b9571fe
  Carl Ritson authored May 17, 2023
  
  0b9571fe
- [X86] Combine constant vector inputs for FMA · c5276f77
  Evgenii Kudriashov authored May 17, 2023
  c5276f77
- [ARM] Remove unused declaration isSafeToDefineLR · c64d0a7f
  Kazu Hirata authored May 16, 2023
  c64d0a7f
- [ARM] Remove unused declaration ARMBaseRegisterInfoARMBaseRegisterInfo::getOpcode · 6a2f52a3
  Kazu Hirata authored May 16, 2023
  
  6a2f52a3
- [Hexagon] Remove getFirstCallerSavedNonParamReg · 901eaf37
  Kazu Hirata authored May 16, 2023
  901eaf37
- [ARM] Remove unused {get,set}StoredByValParamsPadding · ccbe895a
  Kazu Hirata authored May 16, 2023
  ccbe895a
- [Hexagon] Remove unused declaration getLocation · 5b10fa6e
  Kazu Hirata authored May 16, 2023
  5b10fa6e
- [RISCV] Refactor predicates for rvv intrinsic patterns. · 9360926c
  Jianjian GUAN authored May 15, 2023
  9360926c
- [ARM] Remove unused declaration computeIssueWidth · d7aa279e
  Kazu Hirata authored May 16, 2023
  d7aa279e
- [ARM] Remove unused declaration RemapAddSubWithFlags · ae056b56
  Kazu Hirata authored May 16, 2023
  ae056b56
- [Sparc] Make use of GET_SUBTARGETINFO_MACRO (NFC) · d3b9d8b2
  Sergei Barannikov authored May 13, 2023
  d3b9d8b2
- MIPS: allow o32 abi with 64bit CPU and 64 abi with 32bit triple · 7983f8ac
  YunQiang Su authored May 16, 2023
  7983f8ac
May 16, 2023
- Revert "[GlobalIsel][X86] Legalize G_CTPOP and G_CTLZ" · 3ae4265b
  Thorsten Schütt authored May 16, 2023
  3ae4265b
- [GlobalIsel][X86] Legalize G_CTPOP and G_CTLZ · ef1f27d6
  Thorsten Schütt authored May 16, 2023
  ef1f27d6
- ValueTracking: Expand signature of isKnownNeverInfinity/NaN · 86d0b524
  Matt Arsenault authored May 16, 2023
  86d0b524
- [SVE ACLE] Change the lowering of SVE integer builtins · 105d63a2
  Jolanta Jensen authored May 12, 2023
  105d63a2
- [AArch64] Combine add(extract v1i64) into v1i64 add · 198f6a9f
  David Green authored May 16, 2023
  198f6a9f
- [Hexagon] Fix HVX predicates on some intrinsic selection patterns · 41078988
  Krzysztof Parzyszek authored May 16, 2023
  41078988
- [RISCV] Rework how implied SP operands work in the disassembler. NFC · 8f43c3f4
  Craig Topper authored May 16, 2023
  8f43c3f4
- [llvm-objdump][X86] Add @plt symbols for .plt.got · 9e37a7bd
  Fangrui Song authored May 16, 2023
  9e37a7bd
- [AArch64] Use correct IRBuilder in InstCombine hooks · 724f4a5b
  Nikita Popov authored May 16, 2023
  724f4a5b
- [AMDGPU][InferAddressSpaces] Only rewrite address-spaces that can be trivially... · 33da608e
  Juan Manuel MARTINEZ CAAMAÑO authored May 10, 2023
  33da608e
- [AMDGPU] Avoid RegScavenger::forward in copyPhysReg/indirectCopyToAGPR · 64c938e8
  Jay Foad authored May 15, 2023
  64c938e8
- Revert "[GlobalIsel][X86] Legalize G_BSWAP" · e016fe81
  Bjorn Pettersson authored May 16, 2023
  e016fe81
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (multi) · 9b5f1971
  Sander de Smalen authored May 16, 2023
  9b5f1971
- [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (single) · 094005eb
  Sander de Smalen authored May 16, 2023
  094005eb
- [GlobalIsel][X86] Legalize G_BSWAP · 5cafecf9
  Thorsten Schütt authored May 16, 2023
  5cafecf9
- [LoongArch] Move lp64s out of the unimplemented calling conv list · 2cf03140
  Weining Lu authored May 16, 2023
  2cf03140
- [AArch64] Change the type of i64 neon shifts to v1i64 · 8178de32
  David Green authored May 16, 2023
  8178de32
- [GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2 · b5f2bc2d
  Thorsten Schütt authored May 16, 2023
  b5f2bc2d
- [KnownBits] Define and use intersectWith and unionWith · d8229e2f
  Jay Foad authored May 10, 2023
  d8229e2f
- [RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt · 8cf5f730
  Jay Foad authored May 15, 2023
  8cf5f730
- Correct the sort logic in AsmMatcherEmmitter.cpp · 9a24ba23
  Wang, Xin10 authored May 16, 2023
  9a24ba23
- [RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns. · e74bb25d
  Craig Topper authored May 15, 2023
  e74bb25d
- [RISCV] Update RISCVISD::VFWMADD_VLL isel patterns to allow a mask that isn't all ones. · 46cad213
  Craig Topper authored May 15, 2023
  46cad213
- [AMDGPU] Add optional tied-op for wwm-register's epilog spill restore · 08140d16
  Christudasan Devadasan authored May 11, 2023
  08140d16
- [LLVM][Uniformity] Improve detection of uniform registers · fbe1c061
  Sameer Sahasrabuddhe authored May 16, 2023
  fbe1c061