Commits · ee544b8d868d5845798c37200a4b2bd9de889a96 · Roger Ferrer / llvm-epi · GitLab

May 27, 2021
- [NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes · ee544b8d
  Roman Lebedev authored May 28, 2021
  
  ee544b8d
- [PowerPC] Added multiple PowerPC builtins · 62b5df7f
  Quinn Pham authored May 27, 2021
  62b5df7f
- [RISCV] Fix typo, use addImm instead of addReg. · 020df692
  Craig Topper authored May 27, 2021
  
  020df692
- [x86] add tests for extend of vector compare; NFC · 0d5219fe
  Sanjay Patel authored May 27, 2021
  
  0d5219fe
- [NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR · 9712b167
  Roman Lebedev authored May 27, 2021
  9712b167
- Support stripping indirectly referenced DILocations from !llvm.loop metadata · f3869a5c
  Adrian Prantl authored May 26, 2021
  f3869a5c
- [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. · d7ae2438
  Craig Topper authored May 27, 2021
  d7ae2438
- [NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes · bafbec85
  Roman Lebedev authored May 27, 2021
  
  bafbec85
- [CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets · 90d25808
  Simon Pilgrim authored May 27, 2021
  90d25808
- [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell... · 527cd013
  Craig Topper authored May 27, 2021
  527cd013
- [X86] Fold (shift undef, X)->0 for vector shifts by immediate. · a105d302
  Craig Topper authored May 27, 2021
  a105d302
- [X86] Pre-commit tests for D103192. NFC · b5f8ac26
  Craig Topper authored May 27, 2021
  
  b5f8ac26
- [LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass · 21653600
  maekawatoshiki authored May 28, 2021
  21653600
- [RISCV] Add a test case showing incorrect call-conv lowering · 6f4794fe
  Fraser Cormack authored May 27, 2021
  6f4794fe
- GlobalISel: Do not change register types in lowerLoad · e892705d
  Matt Arsenault authored May 18, 2021
  e892705d
- Revert "Emit correct location lists with basic block sections." · 192b4141
  Nico Weber authored May 27, 2021
  192b4141
- AMDGPU/GlobalISel: Fix broken test run line · 34046de0
  Matt Arsenault authored May 20, 2021
  
  34046de0
- [CostModel][X86] AVX512 truncation ops are slower than cost models indicate. · fe8d97cb
  Simon Pilgrim authored May 27, 2021
  fe8d97cb
- [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads · e49d6e16
  Simon Pilgrim authored May 26, 2021
  
  e49d6e16
- VirtRegMap: Preserve LiveDebugVariables · 808dc6f8
  Matt Arsenault authored Oct 29, 2018
  808dc6f8
- AMDGPU/GlobalISel: Lower constant-32-bit zextload/sextload consistently · ee359000
  Matt Arsenault authored May 18, 2021
  ee359000
- [DAGCombine][RISCV] Don't try to trunc-store combined vector stores · b7101e21
  Fraser Cormack authored May 26, 2021
  b7101e21
- [RISCV] Allow passing fixed-length vectors via the stack · 8c73a31c
  Fraser Cormack authored May 13, 2021
  8c73a31c
- [VPlan] Do not sink uniform recipes in sinkScalarOperands. · 38641ddf
  Florian Hahn authored May 27, 2021
  38641ddf
- Add --quiet option to llvm-gsymutil to suppress output of warnings. · 5f2d4b23
  Simon Giesecke authored May 20, 2021
  5f2d4b23
- [ARM] Extra test for reverted WLS memset. NFC · 1d5b976b
  David Green authored May 27, 2021
  
  1d5b976b
- Add triples to a bunch of x86-specific tests that currently fail on PPC · 1546c52d
  Benjamin Kramer authored May 27, 2021
  
  1546c52d
- [Matrix] Include matrix pipeline for new PM in new-pm-defaults.ll. · 9a4506e7
  Florian Hahn authored May 27, 2021
  9a4506e7
- [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs · 772b58a6
  Fraser Cormack authored May 26, 2021
  772b58a6
- [AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv · 0bb60dbe
  Sebastian Neubauer authored May 26, 2021
  0bb60dbe
- [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR. · 9f39ba13
  Amara Emerson authored May 19, 2021
  9f39ba13
- [llvm-objdump] Print the DEBUG type under `--section-headers`. · d82f2a12
  Esme-Yi authored May 27, 2021
  d82f2a12
- Fix non-global-value-max-name-size not considered by LLParser · 8d257627
  Hasyimi Bahrudin authored May 27, 2021
  8d257627
- [RS4GC] Introduce intrinsics to get base ptr and offset · 4d26f41f
  Yevgeny Rouban authored May 27, 2021
  4d26f41f
- [GlobalISel] Don't emit lost debug location remarks when legalizing tail calls · 324af79d
  Jessica Paquette authored May 25, 2021
  324af79d
- Emit correct location lists with basic block sections. · caae5709
  Sriraman Tallam authored May 26, 2021
  caae5709
- [AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE. · 74edfb28
  Amara Emerson authored May 26, 2021
  74edfb28
- [Hexagon] Restore handling of expanding shuffles · 002f5e15
  Krzysztof Parzyszek authored May 22, 2021
  002f5e15
- [tests] Add some basic coverage of multiple exit unrolling · 79c09d5e
  Philip Reames authored May 26, 2021
  
  79c09d5e
May 26, 2021
- [AArch64] Support llvm-mc/llvm-objdump -M no-aliases · 58525825
  Fangrui Song authored May 26, 2021
  58525825