Commits · ef1f7f1d7db1e9bf7e256e208c295b605b014059 · Roger Ferrer / llvm-epi · GitLab

Feb 23, 2021
- Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" · ef1f7f1d
  Jessica Paquette authored Feb 23, 2021
  ef1f7f1d
- [AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars. · 939b5ce7
  Amara Emerson authored Feb 23, 2021
  939b5ce7
- [AArch64] Regenerate check lines for neon-compare-instructions.ll. · fd03e359
  Florian Hahn authored Feb 23, 2021
  fd03e359
- [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. · eb165090
  Craig Topper authored Feb 23, 2021
  eb165090
- [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 · 52bc2e75
  Nicolai Hähnle authored Aug 03, 2020
  52bc2e75
- [X86] Cleanup overflow test check prefixes. NFCI. · 2315410f
  Simon Pilgrim authored Feb 23, 2021
  2315410f
- [AMDGPU] Use divergent addresses for vector loads · fdaa2d02
  Jay Foad authored Feb 19, 2021
  fdaa2d02
- [ARM] do not consider sp as deprecated for ldm/stm · e1c3bf6a
  Sjoerd Meijer authored Feb 23, 2021
  e1c3bf6a
- [ARM] Add pre/post inc tests of various sizes. NFC · ebb6583e
  David Green authored Feb 23, 2021
  
  ebb6583e
- Revert "[WebAssembly] call_indirect issues table number relocs" · 7dc98adb
  Andy Wingo authored Feb 23, 2021
  7dc98adb
- [RISCV] Support insertion of misaligned subvectors · dd68f3cf
  Fraser Cormack authored Feb 18, 2021
  dd68f3cf
- [X86] Support amx-int8 intrinsic. · f8b9035a
  Liu, Chen3 authored Feb 23, 2021
  f8b9035a
- [RISCV] Add test case for missed opportunity use bgez for the canonical form X > -1. NFC · 7195aaa5
  Craig Topper authored Feb 23, 2021
  
  7195aaa5
- Revert "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" · 662402a8
  Jessica Paquette authored Feb 22, 2021
  662402a8
- [Test][AArch64] Test SADDE/SSUBE/UADDE/USUBE narrowing legalization · 05960862
  Cassie Jones authored Feb 22, 2021
  05960862
- [AArch64][GlobalISel] Make overflow legalization use clampScalar · 8b10aa67
  Cassie Jones authored Feb 22, 2021
  8b10aa67
- [X86][AMX] Lower tile copy instruction. · 8f48ddd1
  Luo, Yuanke authored Feb 20, 2021
  8f48ddd1
Feb 22, 2021
- [RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32. · 3231607c
  Craig Topper authored Feb 22, 2021
  3231607c
- [AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt · 867e379c
  Jessica Paquette authored Feb 19, 2021
  867e379c
- [GloblalISel] Support lowering <3 x i8> arguments in multiple parts. · 212d6a95
  Amara Emerson authored Feb 19, 2021
  212d6a95
- [AArch64][GlobalISel] Support lowering <1 x i8> arguments. · 69ce291b
  Amara Emerson authored Feb 18, 2021
  69ce291b
- [WebAssembly] Remap branch dests after fixCatchUnwindMismatches · f47a654a
  Heejin Ahn authored Feb 21, 2021
  f47a654a
- [WebAssembly] Support WasmEHFuncInfo serialization · 51fb5bf4
  Heejin Ahn authored Feb 20, 2021
  51fb5bf4
- [WebAssembly] Split EH MIR tests into two files · 908643ad
  Heejin Ahn authored Feb 21, 2021
  908643ad
- [WebAssembly] Misc. fixes in cfg-stackify-eh.ll · 946a0994
  Heejin Ahn authored Feb 21, 2021
  946a0994
- [AArch64][GlobalISel] Emit G_ASSERT_SEXT for SExt parameters in CallLowering · 95d13c01
  Jessica Paquette authored Feb 17, 2021
  95d13c01
- [AArch64] Adding SHA3 Intrinsics support · 2c25efcb
  Ryan Santhiraraja authored Feb 22, 2021
  2c25efcb
- [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 · 48135180
  Dmitry Preobrazhensky authored Feb 22, 2021
  48135180
- [ARM] Move double vector insert patterns using vins to DAG combine · 21a4faab
  David Green authored Feb 22, 2021
  21a4faab
- [WebAssembly] call_indirect issues table number relocs · 861dbe1a
  Andy Wingo authored Feb 12, 2021
  861dbe1a
- [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr. · 6ff09ce0
  Amara Emerson authored Feb 21, 2021
  6ff09ce0
Feb 21, 2021
- [KnownBits][RISCV] Improve known bits for srem. · 183bbad1
  Craig Topper authored Feb 21, 2021
  183bbad1
- [X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. · b568d3d6
  Simon Pilgrim authored Feb 21, 2021
  
  b568d3d6
- [X86] Regenerate sub.ll test · e7e35e17
  Simon Pilgrim authored Feb 21, 2021
  
  e7e35e17
- [X86] Add 'sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1' tests · 9872cfc5
  Simon Pilgrim authored Feb 21, 2021
  9872cfc5
- [X86] Add common CHECK check-prefix to sub combine tests · 0b372c02
  Simon Pilgrim authored Feb 21, 2021
  
  0b372c02
- [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM. · 1a6c1ac6
  Craig Topper authored Feb 21, 2021
  1a6c1ac6
- [DAG] Match USUBSAT patterns through zext/trunc · 38ab47c8
  Simon Pilgrim authored Feb 21, 2021
  38ab47c8
- [X86][AVX] Fold concat(extract_subvector(v0,c0), extract_subvector(v1,c1)) -> vperm2x128 · a6a258f1
  Simon Pilgrim authored Feb 21, 2021
  a6a258f1
- [X86] Fold bitcast(logic(bitcast(X), Y)) --> logic'(X, bitcast(Y)) for int-int bitcasts · 2885d125
  Simon Pilgrim authored Feb 21, 2021
  2885d125