Commits · ef8707574bbc7d264644d9e6730118cc0addd871 · Roger Ferrer / llvm-epi · GitLab

Aug 24, 2021
- [AArch64][GlobalISel] Legalize narrow scalar FP arithmetic · ef870757
  Jessica Paquette authored Aug 24, 2021
  ef870757
- [MCA] Adding an AMDGPUCustomBehaviour implementation. · e4ebfb57
  Patrick Holland authored Jul 22, 2021
  e4ebfb57
- Revert "[asan] Implemented intrinsic for the custom calling convention similar... · b97ca3ac
  Kirill Stoimenov authored Aug 24, 2021
  b97ca3ac
- [asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86. · 9588b685
  Kirill Stoimenov authored Aug 10, 2021
  9588b685
- [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly... · ce1dc9d6
  Thomas Johnson authored Aug 24, 2021
  ce1dc9d6
- [AArch64][GlobalISel] Legalize + select v2p0 -> v264 G_PTRTOINT · db232de1
  Jessica Paquette authored Aug 23, 2021
  db232de1
- [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld4.* · 67d4dd5c
  Jessica Paquette authored Aug 24, 2021
  67d4dd5c
- [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468) · 307890f8
  Simon Pilgrim authored Aug 24, 2021
  307890f8
- [M68k][AsmParser] Support parsing register masks & fix printing them · 47f52f98
  Ricky Taylor authored Aug 23, 2021
  47f52f98
- [DebugInfo][InstrRef] Fix over-droppage of locations in X86FloatingPoint · 992e21ee
  Jeremy Morse authored Aug 24, 2021
  992e21ee
- [AArch64][SME] Fix v8.6a bf16 NEON instruction predication · e9c8973f
  Cullen Rhodes authored Aug 24, 2021
  e9c8973f
- [ARM] Allow using ';' as asm statement separator in MSVC mode · 039b469b
  Martin Storsjö authored Aug 02, 2021
  039b469b
- [X86] Building constant vector which element type is half will cause assertion fail. · b7795eb6
  Liu, Chen3 authored Aug 24, 2021
  b7795eb6
- [X86] AVX512FP16 instructions enabling 5/6 · c728bd5b
  Wang, Pengfei authored Aug 24, 2021
  c728bd5b
- [AArch64][GlobalISel] Select @llvm.aarch64.neon.ld2.* · 2ec2b25f
  Jessica Paquette authored Aug 23, 2021
  2ec2b25f
Aug 23, 2021
- [TargetMachine] Move COFF special case for ExternalSymbolSDNode from... · ba6e15d8
  Fangrui Song authored Aug 23, 2021
  ba6e15d8
- [CUDA] Add support for CUDA-11.4 · 49d982d8
  Artem Belevich authored Aug 17, 2021
  49d982d8
- [AArch64] Correct store ReadAdrBase operand · 50f4ae58
  David Green authored Aug 23, 2021
  50f4ae58
- [PowerPC][AIX] Set the HasAlloca flag in the AIX Traceback Table only if R31... · b575bbd0
  Zarko Todorovski authored Aug 23, 2021
  b575bbd0
- [AArch64][GlobalISel] Add regbankselect support for G_LLROUND · a2c8e176
  Jessica Paquette authored Aug 23, 2021
  a2c8e176
- [AArch64][GlobalISel] Legalize G_LLROUND for s64 + s32 · fe51f909
  Jessica Paquette authored Aug 23, 2021
  fe51f909
- Recommit "[LoopVectorize][AArch64] Enable ordered reductions by default for AArch64" · d024a015
  Florian Hahn authored Aug 23, 2021
  d024a015
- [AMDGPU] Try to fix a GCC 11 warning · 7a967d90
  Jay Foad authored Aug 23, 2021
  7a967d90
- [AArch64][SME] Support NEON scalar FP instructions in streaming mode · fb82b836
  Cullen Rhodes authored Aug 13, 2021
  fb82b836
- [AArch64][SME] Add predicate for NEON support in streaming mode · cf3c6cca
  Cullen Rhodes authored Aug 18, 2021
  cf3c6cca
- [PowerPC] Use int64_t to represent stack object offset and frame size · 7165e671
  Kai Luo authored Aug 23, 2021
  7165e671
Aug 22, 2021
- [X86] combineMul - move MUL_IMM comment inside function. NFC. · 805fb1f6
  Simon Pilgrim authored Aug 22, 2021
  805fb1f6
- [X86][AVX] matchShuffleAsBlend - use isElementEquivalent to help match broadcast/repeated elements · 352df10a
  Simon Pilgrim authored Aug 22, 2021
  352df10a
- Fix signed/unsigned comparison warning. NFCI. · 96fb3eef
  Simon Pilgrim authored Aug 22, 2021
  
  96fb3eef
- [X86][SSE] lowerVECTOR_SHUFFLE - canonicalize with horizontal ops. · a1c892b4
  Simon Pilgrim authored Aug 22, 2021
  a1c892b4
- [X86] Try to sync HSW + BDW model class defs to simplify comparisons. NFC. · 8533e782
  Simon Pilgrim authored Aug 22, 2021
  8533e782
- [DAGCombiner] Add target hook function to decide folding (mul (add x, c1), c2) · f69fb7ac
  Ben Shi authored Aug 19, 2021
  f69fb7ac
- [X86] AVX512FP16 instructions enabling 4/6 · b088536c
  Wang, Pengfei authored Aug 22, 2021
  b088536c
- [AArch64] Replace unneeded CCAssignToRegWithShadow with CCAssignToReg · 0473e9f4
  Fangrui Song authored Aug 21, 2021
  0473e9f4
Aug 21, 2021
- [TargetMachine] Drop special case for *-win32-macho · a83d99c5
  Fangrui Song authored Aug 21, 2021
  a83d99c5
- [TargetMachine] Simplify shouldAssumeDSOLocal. NFC · c5ee3123
  Fangrui Song authored Aug 21, 2021
  
  c5ee3123
- [ARM] Fix VQDMULH fold for scalar smin · 605489d5
  David Green authored Aug 21, 2021
  605489d5
- [AArch64][GlobalISel] Add legalizer support for the @llvm.get.dynamic.area.offset intrinsic. · 3187a4f3
  Amara Emerson authored Aug 20, 2021
  3187a4f3
- [AArch64][GlobalISel] Don't contract cross-bank copies into truncating stores. · 67bf3ac7
  Amara Emerson authored Aug 20, 2021
  67bf3ac7
Aug 20, 2021
- [AArch64][GlobalISel] Legalize non-register-sized scalar G_BITREVERSE · 9e9d7059
  Jessica Paquette authored Aug 18, 2021
  9e9d7059