Commits · f010b1eae58667b3fcb40c9498974a06ba85d894 · Roger Ferrer / llvm-epi · GitLab

Oct 22, 2022
- Revert "[MachineVerifier] Try harder to verify LiveVariables" · f010b1ea
  Jay Foad authored Oct 22, 2022
  f010b1ea
- Avoid repeated checks and context lookup in llvm::Instruction::getAAMetadata · f2e4ba0e
  serge-sans-paille authored Oct 21, 2022
  f2e4ba0e
- [ORC] Add more information to duplicate section error message. · 45b6fe8c
  Lang Hames authored Oct 22, 2022
  45b6fe8c
- [X86] Add AMX-FP16 instructions. · 661881d4
  Xiang1 Zhang authored Oct 22, 2022
  661881d4
Oct 21, 2022
- [ObjCARC] Remove legacy PM versions of optimization passes · 4153f989
  Arthur Eubanks authored Oct 02, 2022
  4153f989
- [llvm-debuginfo-analyzer] (05/09) - Select elements · de1e911f
  Carlos Alberto Enciso authored Oct 21, 2022
  de1e911f
- [HLSL] Remove unused frontend-generated ID · 4c7218e7
  Chris Bieneman authored Oct 21, 2022
  4c7218e7
- [InstCombine] allow more commutative matches for logical-and to select fold · 30730745
  Sanjay Patel authored Oct 21, 2022
  30730745
- [PGO][AIX] Improve dummy var retention and allow -bcdtors:csect linking. · 461a1836
  Wael Yehia authored Oct 20, 2022
  461a1836
- [AArch64][SVE2] Add the SVE2.1 fdot instructions · 4fd2b491
  David Sherwood authored Oct 19, 2022
  4fd2b491
- [RISCV] Add missing vscale x 1 cost model entries and tests. · 02045021
  Craig Topper authored Oct 21, 2022
  02045021
- [AMDGPU] Use VGPR classes in divergent build_vector patterns · 31bd3e6e
  Jay Foad authored Oct 21, 2022
  31bd3e6e
- [MachineVerifier] Try harder to verify LiveVariables · d4650d09
  Jay Foad authored Jul 06, 2022
  d4650d09
- [InstCombine] allow some commutative matches for logical-and to select fold · d7fecf26
  Sanjay Patel authored Oct 21, 2022
  d7fecf26
- [InstCombine] refactor matching code for logical ands; NFCI · f6fc3e23
  Sanjay Patel authored Oct 21, 2022
  f6fc3e23
- [AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions · d3c8aa7a
  Caroline Concatto authored Oct 20, 2022
  d3c8aa7a
- [AArch64][SVE2] Add the SVE2.1 fclamp instructions · d78c3b32
  David Sherwood authored Oct 19, 2022
  d78c3b32
- [AAArch64][Windows] Fix the crash when running ninja check-asan · ec4db1d0
  chenglin.bi authored Oct 21, 2022
  ec4db1d0
- [AArch64] Add SVE2.1 target feature for Armv9-A 2022 Architecture Extension · fcd54586
  David Sherwood authored Oct 18, 2022
  fcd54586
- [TwoAddressInstruction] Fix stale LiveVariables info in processStatepoint · 33f78d09
  Jay Foad authored Oct 21, 2022
  33f78d09
- [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector · 3bee2fb2
  Caroline Concatto authored Oct 21, 2022
  3bee2fb2
- [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers · 830b5e82
  Caroline Concatto authored Oct 20, 2022
  830b5e82
- [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources · fc0cde8a
  Caroline Concatto authored Oct 20, 2022
  fc0cde8a
- [InstCombine] match logical and/or more generally in fold to select · bf75e937
  Sanjay Patel authored Oct 21, 2022
  bf75e937
- [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers · 1e4f82c2
  Caroline Concatto authored Oct 17, 2022
  1e4f82c2
- [MachineCombiner][RISCV] Relax optimization level requirement · 14a5b9cd
  Anton Sidorenko authored Oct 19, 2022
  14a5b9cd
- [ModuleSummaryAnalysis] Use helper methods to check readnone/readonly (NFC) · eb470e67
  Nikita Popov authored Oct 21, 2022
  eb470e67
- [IndVars] Forget SCEV for value after simplifying condition. · fd236772
  Florian Hahn authored Oct 21, 2022
  fd236772
- [IR] Add support for memory attribute · e9754f02
  Nikita Popov authored Oct 10, 2022
  e9754f02
- [Bitcode] Remove redundant intrinsic remangling (NFCI) · c0283297
  Nikita Popov authored Oct 21, 2022
  c0283297
- [X86] Fold scalar_to_vector(i64 zext(x)) -> bitcast(vzext_movl(scalar_to_vector(i32 x))) · 5ca77541
  Simon Pilgrim authored Oct 21, 2022
  5ca77541
- [LoongArch] Stack realignment support · daf067da
  wanglei authored Oct 21, 2022
  daf067da
- [ARM] Fix the type for v4f16 duplane · fb76d2ce
  David Green authored Oct 21, 2022
  fb76d2ce
- [AutoUpgrade] Fix remangling when upgrading struct return type · c8938809
  Nikita Popov authored Oct 21, 2022
  c8938809
- [Verifier] Relieve intrinsics parameter alignment size constrain · 6ade6d25
  Luo, Yuanke authored Oct 20, 2022
  6ade6d25
- [LoongArch] Modify ParserMethod for the simm26_b operand type · 67902920
  wanglei authored Oct 21, 2022
  67902920
- [LLParser] Remove redundant remangling (NFCI) · befb731b
  Nikita Popov authored Oct 21, 2022
  befb731b
- [AutoUpgrade] Fix length check for intrinsic upgrade · d25ef094
  Nikita Popov authored Oct 21, 2022
  d25ef094
- [VPlan] Print predicates for widened cmp instructions (NFC). · 7eb4ec1c
  Florian Hahn authored Oct 21, 2022
  
  7eb4ec1c
- [AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR · 1809414f
  Pierre van Houtryve authored Oct 19, 2022
  1809414f