Commits · f1388ef006fa87b5799e4bb7cc0662e0b644b35d · Roger Ferrer / llvm-epi · GitLab

Jan 15, 2017
- [AVX-512] Remove unnecessary duplicate broadcast patterns. NFC · f1388ef0
  Craig Topper authored Jan 15, 2017
  f1388ef0
- [AVX-512] Replicate some broadcast patterns to VLX and disable the AVX2... · 52317e8b
  Craig Topper authored Jan 15, 2017
  52317e8b
- [X86] Remove untested MOVDDUP patterns. · c294cff8
  Craig Topper authored Jan 15, 2017
  c294cff8
Jan 14, 2017
- [TargetLowering] Simplfiy a bit. NFCI. · 76de68ea
  Davide Italiano authored Jan 14, 2017
  76de68ea
- [CostModel][X86] Updated vXi64 ASHR costs on AVX512 targets now that D28604 has landed · d419b73a
  Simon Pilgrim authored Jan 14, 2017
  d419b73a
- [X86][XOP] Added support for VPMADCSWD 'extend+hadd' IFMA patterns · 8e5ecf8a
  Simon Pilgrim authored Jan 14, 2017
  8e5ecf8a
- [X86][XOP] Added support for VPMACSDQH/VPMACSDQL 'extension' IFMA patterns · b290805e
  Simon Pilgrim authored Jan 14, 2017
  b290805e
- [X86][XOP] Added support for VPMACSWW/VPMACSDD 'lossy' IFMA patterns · a1631749
  Simon Pilgrim authored Jan 14, 2017
  a1631749
- [AVX-512] Teach two address instruction pass to replace masked move... · 63e2cd6c
  Craig Topper authored Jan 14, 2017
  63e2cd6c
- [AVX-512] Replace V_SET0 in AVX-512 patterns with AVX512_128_SET0. Enhance... · 09b7e0f0
  Craig Topper authored Jan 14, 2017
  09b7e0f0
- [X86] Simplify the code that calculates a scaled blend mask. We don't need a second loop. · 9cc685a5
  Craig Topper authored Jan 14, 2017
  9cc685a5
- [AVX-512] Change blend mask in lowerVectorShuffleAsBlend to a 64-bit value.... · 9850210d
  Craig Topper authored Jan 14, 2017
  9850210d
Jan 13, 2017
- "Use" lambda captures which are otherwise only used in asserts. NFC · 41cecba8
  David L. Jones authored Jan 13, 2017
  41cecba8
- [NVPTX] Added support for half-precision floating point. · 64dc9be7
  Artem Belevich authored Jan 13, 2017
  64dc9be7
- [AMDGPU] Implement f16 fcopysign and fcopysign(f32, f64) · 7d882755
  Konstantin Zhuravlyov authored Jan 13, 2017
  7d882755
- [NVPTX] Only lower sin/cos to approximate instructions if unsafe math is allowed. · d109f465
  Artem Belevich authored Jan 13, 2017
  d109f465
- Remove unused lambda captures. NFC · 17d266bc
  Malcolm Parsons authored Jan 13, 2017
  17d266bc
- Revert r291903 and r291898. Reason: they break check-lld on the bots. · 1ed7896c
  Ivan Krasin authored Jan 13, 2017
  1ed7896c
- ARM: match GCC's behaviour for builtins · 6ef45916
  Saleem Abdulrasool authored Jan 13, 2017
  6ef45916
- Apply clang-tidy's performance-unnecessary-value-param to LLVM. · 061f4a5f
  Benjamin Kramer authored Jan 13, 2017
  061f4a5f
- [globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans · d6a1831e
  Daniel Sanders authored Jan 13, 2017
  d6a1831e
- [X86][AVX512] Add support for variable ASHR v2i64/v4i64 support without VLX · 7f2a6d5e
  Simon Pilgrim authored Jan 13, 2017
  7f2a6d5e
- [aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegisterBankInfo. NFC. · 21ac840f
  Daniel Sanders authored Jan 13, 2017
  21ac840f
- [aarch64][globalisel] Refactor getRegBankBaseIdxOffset() to remove the power-of-2 assumption. NFC · f81cf47e
  Daniel Sanders authored Jan 13, 2017
  f81cf47e
- [ARM] Enable objdump to construct triple for ARM · 770ceb69
  Sam Parker authored Jan 13, 2017
  770ceb69
- [aarch64][globalisel] Move data into <Target>GenRegisterBankInfo. NFC. · 438a1ecc
  Daniel Sanders authored Jan 13, 2017
  438a1ecc
- [ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFC · a2c59149
  Diana Picus authored Jan 13, 2017
  a2c59149
- [ARM] CodeGen: Remove AddDefaultCC. NFC. · 8a73f556
  Diana Picus authored Jan 13, 2017
  8a73f556
- [CodeGen] Rename MachineInstrBuilder::addOperand. NFC · 116bbab4
  Diana Picus authored Jan 13, 2017
  116bbab4
- [ARM] CodeGen: Remove AddDefaultPred. NFC. · 4f8c3e18
  Diana Picus authored Jan 13, 2017
  4f8c3e18
- [X86][AVX512] Adding missing shuffle lowering to blend mask instructions · 558a4d84
  Michael Zuckerman authored Jan 13, 2017
  558a4d84
- [AVX-512] Remove unmasked BLENDM instructions from the wrong load folding... · 1ec84c2a
  Craig Topper authored Jan 13, 2017
  1ec84c2a
- [X86] Move some entries in the load folding tables to move appropriate grouping. NFC · 46b6ecf4
  Craig Topper authored Jan 13, 2017
  46b6ecf4
- [PowerPC] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). · 8187c192
  Eugene Zelenko authored Jan 13, 2017
  8187c192
Jan 12, 2017
- [X86] Replace AND+IMM64 with SRL/SHL · f02ac0ee
  Nikolai Bozhenov authored Jan 12, 2017
  f02ac0ee
- [X86] Tune bypassing of slow division for Intel CPUs · 6bdf92ce
  Nikolai Bozhenov authored Jan 12, 2017
  6bdf92ce
- AMDGPU: Skip fneg/select combine if it can fold into other · 45337df0
  Matt Arsenault authored Jan 12, 2017
  45337df0
- AMDGPU: Fold free fneg into sin · 31c039ef
  Matt Arsenault authored Jan 12, 2017
  31c039ef
- ARM: slightly more table driven libcall setup · 555e5980
  Saleem Abdulrasool authored Jan 12, 2017
  555e5980
- AMDGPU: Fold fneg into fmul_legacy · a8c325e2
  Matt Arsenault authored Jan 12, 2017
  a8c325e2