Commits · f2b4b2ebe7a3c1d85a138fc729faf5c3ccb2e941 · Roger Ferrer / llvm-epi · GitLab

Apr 05, 2022
- Reverting changes to correct the commit message · f2b4b2eb
  Biplob Mishra authored Apr 05, 2022
  
  f2b4b2eb
- [AArch64] Set maximum VF with shouldMaximizeVectorBandwidth · 64b6192e
  Jingu Kang authored Apr 05, 2022
  64b6192e
- [ARM][AArch64] Optimize pattern for converting a half word byte swap in a... · afca54f0
  Biplob Mishra authored Apr 05, 2022
  afca54f0
- [AArch64] Make PMMIR_EL1 read-only. · 82bd0bd2
  Simon Tatham authored Apr 05, 2022
  82bd0bd2
- Revert "[CodeGen] Async unwind - add a pass to fix CFI information" · 0320115c
  Muhammad Omair Javaid authored Apr 05, 2022
  0320115c
- [M68k] Adopt VarLenCodeEmitter for move instructions · 18b38ff6
  Min Hsu authored Dec 18, 2021
  18b38ff6
- [X86] Improve x86-partial-reduction to support abs intrinsic · ca33d74c
  Wei Xiao authored Mar 30, 2022
  ca33d74c
- [AArch64] Alter mull buildvectors(ext(..)) combine to work on shuffles · 3b983359
  David Green authored Apr 04, 2022
  3b983359
Apr 04, 2022
- [X86] Add XOR(X, MIN_SIGNED_VALUE) -> ADD(X, MIN_SIGNED_VALUE) isel patterns (PR52267) · ffe0cc82
  Simon Pilgrim authored Apr 04, 2022
  ffe0cc82
- [AMDGPU] Ignore debug use during PreRARematerialize stage in scheduling pass · 45c2371c
  Vang Thao authored Apr 04, 2022
  45c2371c
- [AArch64] Increase cost of v2i64 multiplies · 750bf358
  David Green authored Apr 04, 2022
  750bf358
- [CodeGen] Async unwind - add a pass to fix CFI information · 980c3e6d
  Momchil Velikov authored Apr 04, 2022
  980c3e6d
- [AArch64] Teach the costmodel about widening muls · 2abaa027
  David Green authored Apr 04, 2022
  2abaa027
- [X86] Support optional NOT stages in the AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) fold · 623d4b57
  Simon Pilgrim authored Apr 04, 2022
  623d4b57
- [M68k] Adopt VarLenCodeEmitter for shift / rotate instructions · fccdc561
  Min Hsu authored Dec 17, 2021
  fccdc561
Apr 03, 2022
- [AArch64] Remove unsued WideningBaseCost. NFC · 3c88ff44
  David Green authored Apr 03, 2022
  3c88ff44
- [X86] lowerShuffleAsRepeatedMaskAndLanePermute - allow v16i32 sub-lane permutes for v64i8 shuffles · fbfd78f7
  Simon Pilgrim authored Apr 03, 2022
  fbfd78f7
Apr 02, 2022
- [LoongArch] Fix instruction definition · cd85ea94
  wanglei authored Apr 02, 2022
  cd85ea94
- [RISCV] Add lowering for vp.fptoui and vp.uitofp. · d970e96c
  Craig Topper authored Apr 01, 2022
  d970e96c
Apr 01, 2022
- [RISCV][AMDGPU][TargetLowering] Special case overflow expansion for (uaddo X, 1). · fa630e75
  Craig Topper authored Apr 01, 2022
  fa630e75
- [DAG] Add llvm::isMinSignedConstant helper. NFC · 76cd11f3
  Simon Pilgrim authored Apr 01, 2022
  76cd11f3
- [X86] matchAddressRecursively - add XOR(X, MIN_SIGNED_VALUE) handling · c64f37f8
  Simon Pilgrim authored Apr 01, 2022
  c64f37f8
- [X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) (RECOMMITTED) · b8652fbc
  Simon Pilgrim authored Apr 01, 2022
  b8652fbc
- Revert rGa5f637bcbb7d1e08ce637f113fc117c3f4b2b110 "[X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y))" · 5a457bd2
  Simon Pilgrim authored Apr 01, 2022
  5a457bd2
- [X86] lowerShuffleAsRepeatedMaskAndLanePermute - allow 64-bit sublane... · 9afa6811
  Simon Pilgrim authored Apr 01, 2022
  9afa6811
- [X86] Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) · a5f637bc
  Simon Pilgrim authored Apr 01, 2022
  a5f637bc
- [AMDGPU] Only count global-to-global as indirect accesses · c246b7bd
  Jay Foad authored Mar 31, 2022
  c246b7bd
- [X86] Add getBT helper node for attempting to create a X86ISD::BT node · 3245cfb8
  Simon Pilgrim authored Apr 01, 2022
  3245cfb8
- Revert rGff2d1bb2b749bd8a5697c25d2380b7c97a59ae06 "[X86] Add getBT helper node... · 919b6570
  Simon Pilgrim authored Apr 01, 2022
  919b6570
- [X86] Add getBT helper node for attempting to create a X86ISD::BT node · ff2d1bb2
  Simon Pilgrim authored Apr 01, 2022
  ff2d1bb2
- [X86] lowerV8I16Shuffle - use explicit SmallVector<SDValue, 4> width to avoid... · cb5c4a59
  Simon Pilgrim authored Apr 01, 2022
  cb5c4a59
- [CSKY] AsmBackend: Wrap Inst.dump() in LLVM_DEBUG · 481e2dde
  Kees Cook authored Mar 31, 2022
  481e2dde
- [X86] Set frame-setup/frame-destroy on prologue/epilogue CFI instructions · ac6878b3
  Fangrui Song authored Mar 31, 2022
  ac6878b3
- [RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub · 62dd3674
  Lian Wang authored Mar 31, 2022
  62dd3674
- Target: Use getPointerSizeInBits instead of 8 * getPointerSize · 14744622
  Matt Arsenault authored Mar 31, 2022
  
  14744622
- X86/GlobalISel: Use LLT form of getMachineMemOperand · f635be30
  Matt Arsenault authored Mar 31, 2022
  
  f635be30
- MSP430: Avoid using getPointerSize/getPointerTy · f942cde6
  Matt Arsenault authored Mar 31, 2022
  f942cde6
Mar 31, 2022
- ARM/GlobalISel: Get pointer type from value instead of getPointerSize · 0fb6856a
  Matt Arsenault authored Mar 30, 2022
  0fb6856a
- [PowerPC] Fix lowering of byval parameters for sizes greater than 8 bytes. · 585c85ab
  Stefan Pintilie authored Mar 31, 2022
  585c85ab
- [PowerPC] Set the special DSCR with a compiler option. · 2e55bc9f
  Stefan Pintilie authored Mar 31, 2022
  2e55bc9f