Commits · f2d2cedab48f07d63b219836fcb7b653c9aeb27b · Roger Ferrer / llvm-epi · GitLab

May 03, 2018
- [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes · f2d2ceda
  Simon Pilgrim authored May 03, 2018
  f2d2ceda
- [PowerPC] add tests for FMF propagation; NFC · e7532d29
  Sanjay Patel authored May 03, 2018
  e7532d29
- [CodeGen][X86][NFC] Copy two selectcc tests from AArch64. · 63ac1936
  Roman Lebedev authored May 03, 2018
  63ac1936
- [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes · f7dd6069
  Simon Pilgrim authored May 03, 2018
  f7dd6069
- ARM: don't try to over-align large vectors as arguments. · 28e0a6f7
  Tim Northover authored May 03, 2018
  28e0a6f7
- Rename invariant.group.barrier to launder.invariant.group · 5dde8094
  Piotr Padlewski authored May 03, 2018
  5dde8094
- [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and... · 93c878c7
  Simon Pilgrim authored May 03, 2018
  93c878c7
- MachineInst support mapping SDNode fast math flags for support in Back End code generation · 7d1b25d0
  Michael Berg authored May 03, 2018
  7d1b25d0
- [PowerPC] Implement isMaskAndCmp0FoldingBeneficial · 01e2e79a
  Nemanja Ivanovic authored May 02, 2018
  01e2e79a
- [PowerPC] No CTR loop if the candidate exiting block is in a different loop · 2139e99e
  Nemanja Ivanovic authored May 02, 2018
  2139e99e
May 02, 2018
- [X86][SNB] Fix scheduling of MMX integer multiply instructions. · 350c22c5
  Simon Pilgrim authored May 02, 2018
  350c22c5
- [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM... · 6732f6ea
  Simon Pilgrim authored May 02, 2018
  6732f6ea
- [AMDGPU] A trivial fix for a buildbot failure caused by "commit... · 07e61234
  Farhana Aleen authored May 02, 2018
  07e61234
- [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes... · 819f218f
  Simon Pilgrim authored May 02, 2018
  819f218f
- Revert "[AMDGPU] performAddCombine should run after DAG is legalized." · 150cb6d9
  Farhana Aleen authored May 02, 2018
  150cb6d9
- [AMDGPU] performAddCombine should run after DAG is legalized. · 2f4100f5
  Farhana Aleen authored May 02, 2018
  2f4100f5
- [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values · e93fd5f1
  Simon Pilgrim authored May 02, 2018
  e93fd5f1
May 01, 2018
- [AMDGPU] Support horizontal vectorization. · e2dfe8a8
  Farhana Aleen authored May 01, 2018
  e2dfe8a8
- [AArch64] Add more tests for 64-bit immediate lowering. · 763d161e
  Eli Friedman authored May 01, 2018
  763d161e
- [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N) · e23173b6
  Vedant Kumar authored May 01, 2018
  e23173b6
- [DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N) · d7117ed0
  Vedant Kumar authored May 01, 2018
  d7117ed0
- [DAGCombiner] Change the SDLoc on split extloads (2/N) · cc7b2a55
  Vedant Kumar authored May 01, 2018
  cc7b2a55
- [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N) · ee4bfcaa
  Vedant Kumar authored May 01, 2018
  ee4bfcaa
- AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago) · 1501af48
  Konstantin Zhuravlyov authored May 01, 2018
  1501af48
- [X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classes · 21caf012
  Simon Pilgrim authored May 01, 2018
  21caf012
- [X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes · 5269167f
  Simon Pilgrim authored May 01, 2018
  5269167f
- [DAG] add test to show FMF mismatch between IR and DAG; NFC · 5727011f
  Sanjay Patel authored May 01, 2018
  5727011f
- [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes · dd8eae12
  Simon Pilgrim authored May 01, 2018
  dd8eae12
- Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions" · 3d562fb9
  Simon Dardis authored May 01, 2018
  3d562fb9
- [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes · 57f2b185
  Simon Pilgrim authored May 01, 2018
  57f2b185
- [X86] Correct spill slot size. · d4c58400
  Andrea Di Biagio authored May 01, 2018
  d4c58400
- [X86] movdiri and movdir64b instructions · c8ded04e
  Gabor Buella authored May 01, 2018
  c8ded04e
Apr 30, 2018
- [LivePhysRegs] Remove registers clobbered by regmasks from the live set · 1cf329c9
  Krzysztof Parzyszek authored Apr 30, 2018
  1cf329c9
- AMDGPU: Add Vega12 and Vega20 · 0084adc5
  Matt Arsenault authored Apr 30, 2018
  0084adc5
- [MIR] Reset unique MBB numbering in MachineFunction::reset() · 46f838f3
  Roman Tereshin authored Apr 30, 2018
  46f838f3
- [DAGCombiner] rename function attribute for disabling ftrunc transform · 1babf5ff
  Sanjay Patel authored Apr 30, 2018
  1babf5ff
- [SystemZ] Handle SADDO et.al. and ADD/SUBCARRY · c3ec80fe
  Ulrich Weigand authored Apr 30, 2018
  c3ec80fe
- [SystemZ] Do not use glue to represent condition code dependencies · b32f3656
  Ulrich Weigand authored Apr 30, 2018
  b32f3656
- Fix infinite loop after r331115 · 2de9d4ad
  Daniel Sanders authored Apr 30, 2018
  2de9d4ad
- [SystemZ] Improve handling of Select pseudo-instructions · fb56686c
  Ulrich Weigand authored Apr 30, 2018
  fb56686c