Commits · f431a2f2613a142cd1442e9c49c2e760081652a5 · Roger Ferrer / llvm-epi · GitLab

Oct 22, 2018
- [hot-cold-split] Add opt remark on success · f431a2f2
  Teresa Johnson authored Oct 22, 2018
  f431a2f2
- Revert r344930 as it broke some of the bots on Windows. · 036e54d3
  Aaron Ballman authored Oct 22, 2018
  036e54d3
- [SourceMgr][FileCheck] Obey -color by extending WithColor · 279f8a44
  Joel E. Denny authored Oct 22, 2018
  279f8a44
- [hot-cold-split] Add missing FileCheck invocations · 16ce43a2
  Teresa Johnson authored Oct 22, 2018
  16ce43a2
- Revert r344877 "[X86] Stop promoting integer loads to vXi64" · 8d8dcfe6
  Craig Topper authored Oct 22, 2018
  8d8dcfe6
- [test] Relax test/Other/opt-hot-cold-split.ll · ba88ad35
  Vedant Kumar authored Oct 22, 2018
  ba88ad35
- DAG: Change behavior of fminnum/fmaxnum nodes · 687ec75d
  Matt Arsenault authored Oct 22, 2018
  687ec75d
- [InstCombine] add tests for shuffle+insert folds; NFC · 21d8aef0
  Sanjay Patel authored Oct 22, 2018
  21d8aef0
- [X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern · 13c5ab2e
  Roman Lebedev authored Oct 22, 2018
  13c5ab2e
- [llvm-dwarfdump] - Fix win10 build bot failture. · 20923209
  George Rimar authored Oct 22, 2018
  20923209
- [llvm-dwarfdump] - Add the support of parsing .debug_loclists. · 4c7dd9cf
  George Rimar authored Oct 22, 2018
  4c7dd9cf
- [PowerPC][NFC] Fix bugs in r+r to r+i conversion · 674581af
  Nemanja Ivanovic authored Oct 22, 2018
  674581af
- [X86] Add patterns for vector and/or/xor/andn with other types than vXi64. · 290c081d
  Craig Topper authored Oct 22, 2018
  290c081d
- [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when · 3ec99fe2
  Dorit Nuzman authored Oct 22, 2018
  3ec99fe2
Oct 21, 2018
- [X86] Stop promoting integer loads to vXi64 · 321df5b0
  Craig Topper authored Oct 21, 2018
  321df5b0
- [DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016) · e439cc27
  Sanjay Patel authored Oct 21, 2018
  e439cc27
- Schedule Hot Cold Splitting pass after most optimization passes · d9e2e383
  Aditya Kumar authored Oct 21, 2018
  d9e2e383
- [X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 unary shuffle lowering · eb806d5f
  Simon Pilgrim authored Oct 21, 2018
  eb806d5f
- [WebAssembly] Change tabs to spaces in basic-assembly.s · 0ab7245c
  Heejin Ahn authored Oct 21, 2018
  0ab7245c
Oct 20, 2018
- [ORC] Add some more basic sanity tests for the LLJIT. · e433cf1f
  Lang Hames authored Oct 20, 2018
  e433cf1f
- [InstCombine] add test for possible shuffle fold; NFC · ed3da321
  Sanjay Patel authored Oct 20, 2018
  ed3da321
- [CostModel][X86] Add some initial extract/insert subvector shuffle cost tests · acd10b9f
  Simon Pilgrim authored Oct 20, 2018
  acd10b9f
- [SLPVectorizer][X86] Add mul/and/or/xor unrolled reduction tests · 0c35aa11
  Simon Pilgrim authored Oct 20, 2018
  0c35aa11
- [SLPVectorizer] regenerate test checks; NFC · 007416ac
  Sanjay Patel authored Oct 20, 2018
  007416ac
- [CostModel][X86] Add integer vector reduction cost tests · e612ab0c
  Simon Pilgrim authored Oct 20, 2018
  e612ab0c
- DebugInfo: Use base address specifiers more aggressively · 14cfa0dc
  David Blaikie authored Oct 20, 2018
  14cfa0dc
- DebugInfo: Use DW_OP_addrx in DWARFv5 · 2df23a4e
  David Blaikie authored Oct 20, 2018
  2df23a4e
- DebugInfo: Implement debug_rnglists.dwo · 32e09de9
  David Blaikie authored Oct 20, 2018
  32e09de9
- DebugInfo: Use address pool forms in debug_rnglists · c4af8bf2
  David Blaikie authored Oct 20, 2018
  c4af8bf2
- llvm-dwarfdump: Support RLE_addressx and RLE_startx_length in .debug_rnglists · 59ac2064
  David Blaikie authored Oct 20, 2018
  59ac2064
- DebugInfo: Use debug_addr for non-dwo addresses in DWARF 5 · 161dd3c1
  David Blaikie authored Oct 20, 2018
  161dd3c1
- [WebAssembly] Implement vector sext_inreg and tests with comparisons · 5ea17d45
  Thomas Lively authored Oct 20, 2018
  5ea17d45
- [WebAssembly] Custom lower i64x2 constant shifts to avoid wrap · 55735d52
  Thomas Lively authored Oct 20, 2018
  55735d52
- [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again) · 8d6ff4c0
  Roman Tereshin authored Oct 20, 2018
  8d6ff4c0
- [llvm-objdump] Fix --file-headers (-f) option · 8d947bad
  Petar Jovanovic authored Oct 19, 2018
  8d947bad
Oct 19, 2018
- [LoopVectorize] Loop vectorization for minimum and maximum · 8a91cf1c
  Thomas Lively authored Oct 19, 2018
  8a91cf1c
- AMDGPU: Add support pattern for SUB of one bit · f95f763e
  Changpeng Fang authored Oct 19, 2018
  f95f763e
- [GISel]: Allow PHIs to be DCEd · cd04e366
  Aditya Nandakumar authored Oct 19, 2018
  cd04e366
- [DWARF] Make llvm-dwarfdump display location lists in a .dwp file correctly. Fixes PR38990. · 6214c11c
  Wolfgang Pieb authored Oct 19, 2018
  6214c11c
- [WebAssembly] Handle undefined lane indices in SIMD patterns · 11a332d0
  Thomas Lively authored Oct 19, 2018
  11a332d0