Commits · f467aa1b6477585829f973e3adf8c35b6e99dc47 · Roger Ferrer / llvm-epi · GitLab

Feb 28, 2022
- [Support] Add CSKY target parser and attributes parser · 21bce900
  Zi Xuan Wu authored Feb 15, 2022
  21bce900
- [RISCV] Optimize (sext.w, srli) to sraiw with Zba. · 7f811ce1
  Chenbing Zheng authored Feb 28, 2022
  7f811ce1
Feb 27, 2022
- [RISCV] Fix parseBareSymbol to not double-parse top-level operators · 6aa8521f
  Jessica Clarke authored Feb 27, 2022
  6aa8521f
- [X86][SSE] Attempt to lower vec_reduce_add patterns with PSADBW for zero-extended vXi8 sources · 2b46417a
  Simon Pilgrim authored Feb 27, 2022
  2b46417a
- [AMDGPU] Remove redundant isVALU in SIPreEmitPeephole. NFC · 2bbe6506
  Carl Ritson authored Feb 27, 2022
  2bbe6506
Feb 26, 2022
- Use RegisterInfo::regsOverlaps instead of checking aliases · 1de11fe3
  Benjamin Kramer authored Feb 26, 2022
  1de11fe3
Feb 25, 2022
- mark getTargetTransformInfo and getTargetIRAnalysis as const · c4b1a63a
  Jameson Nash authored Feb 25, 2022
  c4b1a63a
- [AMDGPU][NFC]: Emit metadata for hidden_heap_v1 kernarg · ca62b1db
  Changpeng Fang authored Feb 25, 2022
  ca62b1db
- [PowerPC][NFC] Split out the MMA instructions from the P10 instructions. · 0625aed2
  Stefan Pintilie authored Feb 25, 2022
  0625aed2
- Avoid comparisons between types of different widths in a loop condition to... · bf60a1c5
  Aakanksha authored Feb 25, 2022
  bf60a1c5
- [SVE] Add missing splat patterns for bfloat vectors. · 16ee1029
  Paul Walker authored Feb 24, 2022
  16ee1029
- [PowerPC][NFC] Add file info and license that was missing from this file. · 4fbe60fd
  Stefan Pintilie authored Feb 25, 2022
  4fbe60fd
- [NFC][SVE] Refactor SelectSVEAddSubImm to match SelectSVECpyDupImm. · e109ce91
  Paul Walker authored Feb 24, 2022
  e109ce91
- [SVE] Refactor complex immediate pattern used by CPY/DUP. · 7ab78f34
  Paul Walker authored Feb 23, 2022
  7ab78f34
- [X86] Combine ADC(ADD(X,Y),0,Carry) -> ADC(X,Y,Carry) · eb1ff70f
  Pawe Bylica authored Feb 25, 2022
  eb1ff70f
- [RISCV] Fix a mistake in PostprocessISelDAG · 865fe131
  Haocong.Lu authored Feb 25, 2022
  865fe131
- [SVE] Don't custom lower constant predicate ISD:SPLAT_VECTOR operations. · 8ca5be93
  Paul Walker authored Feb 22, 2022
  8ca5be93
- [AArch64] Async unwind - Refactor generation of shadow call stack prologue/epilogue · 20a093e2
  Momchil Velikov authored Feb 25, 2022
  20a093e2
- [IR] Use CallBase::getParamElementType() (NFC) · 87ebd9a3
  Nikita Popov authored Feb 25, 2022
  87ebd9a3
- Revert rG87753cebf5f861eee418d6bce155dfa0b00f9878 "[X86]... · 748bf545
  Simon Pilgrim authored Feb 25, 2022
  748bf545
- [NVPTX][AsmPrinter] Emit .attribute(.managed) for global variable declarations · 3fe6f938
  Kristina Bessonova authored Feb 25, 2022
  3fe6f938
- [SystemZ] [z/OS] Add support for generating huge (1 MiB) stack frames in XPLINK64 · eb3e09c9
  Neumann Hon authored Feb 25, 2022
  eb3e09c9
- [RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm · b20e80aa
  Chenbing Zheng authored Feb 25, 2022
  b20e80aa
- [RISCV] Update computeTargetABI from llc as well as clang · 4e115b7d
  Zakk Chen authored Feb 24, 2022
  4e115b7d
- [RISCV] Add schedule class for Zbt extension · f37d21ed
  lian wang authored Feb 16, 2022
  f37d21ed
- [AMDGPU] Extend pre-emit peephole to redundantly masked VCC · 565af157
  Carl Ritson authored Feb 25, 2022
  565af157
- [OpaquePtr][AArch64] Use load/store value type instead of pointer type for ldnt1/stnt1 alignment · 6aa285eb
  Arthur Eubanks authored Feb 24, 2022
  
  6aa285eb
- [RISCV] Change rvv version to 1.0 and remove ratify notice · 0d058ed3
  Qihan Cai authored Feb 25, 2022
  0d058ed3
- [RISCV] Add 'i64' to some isel so tablegen will remove them for RV32. NFC · 506ac296
  Craig Topper authored Feb 24, 2022
  506ac296
Feb 24, 2022
- [AMDGPU] Divergence-driven instruction selection for bitreverse · 05d79e35
  Jay Foad authored Feb 14, 2022
  05d79e35
- [AMDGPU] Extend SILoadStoreOptimizer to handle global stores · 3279e440
  Stanislav Mekhanoshin authored Feb 22, 2022
  3279e440
- [AArch64] Async unwind - Always place the first LDP at the end when ReverseCSRRestoreSeq is true · 17e85cd4
  Momchil Velikov authored Feb 24, 2022
  17e85cd4
- [AMDGPU] Fix combined MMO in load-store merge · cefa1c5c
  Stanislav Mekhanoshin authored Feb 22, 2022
  cefa1c5c
- [X86] Introduce x86-cmov-converter-force-all · e38fc14c
  Amir Ayupov authored Feb 15, 2022
  e38fc14c
- [AArch64] Async unwind - helper functions to decide on CFI emission · 25e92920
  Momchil Velikov authored Feb 24, 2022
  25e92920
- [AArch64] Async unwind - do not schedule frame setup/destroy · fd7e59f0
  Momchil Velikov authored Feb 24, 2022
  fd7e59f0
- [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X). · a975ca97
  Craig Topper authored Feb 24, 2022
  a975ca97
- [X86] LowerRotate - enable v8i16 ROTL/ROTR on all pre-SSE41 targets · a636801a
  Simon Pilgrim authored Feb 24, 2022
  a636801a
- [X86] SimplifyDemandedVectorEltsForTargetNode - add X86ISD::ANDNP handling · 0ea50bee
  Simon Pilgrim authored Feb 24, 2022
  
  0ea50bee
- [NFC][RISCV] Reuse ISD::NodeType in float extension · 78b5f0fb
  Shao-Ce SUN authored Feb 24, 2022
  78b5f0fb