Commits · f57f086714bc7a1399acf05d5ca1d665237cd725 · Roger Ferrer / llvm-epi · GitLab

Dec 01, 2022
- [AArch64TargetParser] getArchFeatures -> getArchFeature · f57f0867
  Tomas Matheson authored Nov 18, 2022
  f57f0867
- [X86] Remove unnecessary INTO overrides from znver1/znver2 model · 4d98eb21
  Simon Pilgrim authored Nov 30, 2022
  4d98eb21
- [X86] Remove unnecessary VPERMPS/VPERMDrr overrides from znver3 model · 19d1e4cd
  Simon Pilgrim authored Nov 30, 2022
  19d1e4cd
- [X86] Remove unnecessary XADD*rr overrides from bdver2 model · 74c0f57d
  Simon Pilgrim authored Nov 30, 2022
  74c0f57d
- Revert "[AArch64][SME]: Generate streaming-compatible code for ld2-alloca." · 4a5ccf4e
  David Sherwood authored Dec 01, 2022
  4a5ccf4e
- [RISCV] Use Register instead of unsigned. NFC · 25ddac98
  Craig Topper authored Nov 30, 2022
  
  25ddac98
- [X86] Add ExpandLargeFpConvert Pass and enable for X86 · 89f36dd8
  Freddy Ye authored Dec 01, 2022
  89f36dd8
- [RISCV] Add ANDI to getRegAllocationHints. · df7ab6a5
  Craig Topper authored Nov 30, 2022
  
  df7ab6a5
- [RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC · 7899cc3c
  Craig Topper authored Nov 30, 2022
  
  7899cc3c
- [AArch64][SME][NFC]: Enable lowering truncate for enhancement. · 2bda5a62
  Hassnaa Hamdi authored Dec 01, 2022
  2bda5a62
- [AArch64][SME]: Scalarize masked gather/scatter in streaming mode. · 942f3ee4
  Hassnaa Hamdi authored Nov 29, 2022
  942f3ee4
- [AArch64][SME]: Generate streaming-compatible code for ld2-alloca. · 279c0a83
  Hassnaa Hamdi authored Nov 30, 2022
  279c0a83
- [AMX] Support AMX-FP16 new intrinsic interface · 94c5df8a
  Xiang1 Zhang authored Dec 01, 2022
  94c5df8a
- [LoongArch] Add remaining intrinsics for CRC check instructions · 62440161
  gonglingqin authored Dec 01, 2022
  62440161
Nov 30, 2022
- [RISCV][Codegen] Account for LMUL in Vector floating-point instructions · e9f2bac9
  Michael Maitland authored Nov 03, 2022
  e9f2bac9
- [RISCV] Inline RISCVFrameLowering::adjustReg out of existance [nfc] · 14d99343
  Philip Reames authored Nov 30, 2022
  14d99343
- [RISCV] Adjust code to fallthrough to a single adjustReg callsite [nfc] · c0692c08
  Philip Reames authored Nov 30, 2022
  c0692c08
- [RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI. · a8c79121
  Craig Topper authored Nov 30, 2022
  a8c79121
- [RISCV] Merge two versions of adjustReg on TRI [nfc] · 1f04ac54
  Philip Reames authored Nov 30, 2022
  1f04ac54
- [AMDGPU] Use s_cmp instead of s_cmpk · 3d9e2260
  Jay Foad authored Nov 30, 2022
  3d9e2260
- [RISCV] Reuse and generalize adjustReg from another spot in frame lowering [nfc] · 80fcf992
  Philip Reames authored Nov 30, 2022
  80fcf992
- [RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants) · ac1ec9e2
  Philip Reames authored Nov 30, 2022
  ac1ec9e2
- [RISCV][TTI] Account for constant materialization cost when costing arithmetic operations · 7d82c994
  Philip Reames authored Nov 30, 2022
  7d82c994
- [AArch64] Assembly support for VMSA · 7fea6f2e
  Tomas Matheson authored Nov 24, 2022
  7fea6f2e
- [AMDGPU] Remove todo about vector types · 53efce30
  Sebastian Neubauer authored Nov 30, 2022
  53efce30
- [AArch64] Don't treat SVE scalable extends as free widening instructions · f2a92db2
  David Green authored Nov 30, 2022
  f2a92db2
- [RISCV] Add cost model for fixed broadcast shuffle · 0e6f0b7c
  ShihPo Hung authored Nov 30, 2022
  0e6f0b7c
- [X86] Add missing PFM port mappings for Core2/Nehalem · b0468e3e
  Simon Pilgrim authored Nov 29, 2022
  b0468e3e
- [CodeGen][X86] Crash fixes for "patchable-function" pass · 3f3438a5
  Sylvain Audi authored Nov 04, 2022
  3f3438a5
- [AMDGPU] Use aperture registers instead of S_GETREG · a88deb4b
  Pierre van Houtryve authored Nov 28, 2022
  a88deb4b
- [AMDGPU][MC][GFX11] Disable non-VGPR src operands for VOP3_DPP variants of fmac instructions · f2d589ea
  Dmitry Preobrazhensky authored Nov 30, 2022
  f2d589ea
- X86: relax EFLAGS liveness check when generating stack probes. · b32280ba
  Tim Northover authored Nov 22, 2022
  b32280ba
- [AMDGPU] Fix location of line break in VOPC instruction table · 2b97b069
  Jay Foad authored Nov 30, 2022
  
  2b97b069
- AMDGPU: Fixup tests · 4e79764f
  Nicolai Hähnle authored Nov 30, 2022
  
  4e79764f
- AMDGPU: Remove ImagePSV and move images to addrspace 7 · b7f44f7c
  Nicolai Hähnle authored Nov 29, 2022
  b7f44f7c
- [LoongArch] Add codegen support for atomicrmw min/max operation on LA64 · 5f9b4d8b
  gonglingqin authored Nov 30, 2022
  5f9b4d8b
- [RISCV] Remove lmuls argument in Sched class · 2b6910e1
  Pengcheng Wang authored Nov 30, 2022
  2b6910e1
- [AMDGPU] Remove AMDGPUISelDAGToDAG::isKnownNeverNaN · 851176c7
  Thomas Symalla authored Nov 29, 2022
  851176c7
- [RISCV] Preserve chain output when selecting splat as x0 strided load. · 9e0f9f11
  Craig Topper authored Nov 29, 2022
  9e0f9f11
- [RISCV][CodeGen] Account for LMUL for Vector Fixed-Point Arithmetic Instructions · 26e44d4a
  Michael Maitland authored Nov 03, 2022
  26e44d4a