Commits · f69e090d7dca6bf2786145a9e97b0a7ddb3b514a · Roger Ferrer / llvm-epi · GitLab

Sep 16, 2020
- [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register. · 2ce1a697
  Craig Topper authored Sep 15, 2020
  2ce1a697
Aug 26, 2020
- [X86] Add assembler support for .d32 and .d8 mnemonic suffixes to control displacement size. · 09288bcb
  Craig Topper authored Aug 26, 2020
  09288bcb
Aug 03, 2020
- [X86] support .nops directive · c6334db5
  Jian Cai authored Jul 30, 2020
  c6334db5
Aug 01, 2020
- [X86] Add assembler support for {disp8} and {disp32} to control the size of... · e297d928
  Craig Topper authored Aug 01, 2020
  e297d928
Jul 30, 2020
- [X86] Parse and ignore .arch directives · d2c22487
  Fangrui Song authored Jul 30, 2020
  d2c22487
- [X86] Teach the assembler parser to handle a '*' between segment register and... · 9611ee5f
  Craig Topper authored Jul 29, 2020
  9611ee5f
Jul 28, 2020
- [X86] Add support for {disp32} to control size of jmp and jcc instructions in the assembler · 25f193fb
  Craig Topper authored Jul 27, 2020
  25f193fb
- [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode. · a0ebac52
  Craig Topper authored Jul 27, 2020
  a0ebac52
Jul 20, 2020
- [llvm-readobj] Update tests because of changes in llvm-readobj behavior · b36a3e61
  Elvina Yakubova authored Jul 20, 2020
  b36a3e61
Jul 16, 2020
- [X86] Allow lsl/lar to be parsed with a GR16, GR32, or GR64 as source register. · 71b49aa4
  Craig Topper authored Jul 15, 2020
  71b49aa4
- [X86] Teach assembler parser to accept lsl and lar with a 64 or 32 source... · 3c2a56a8
  Craig Topper authored Jul 15, 2020
  3c2a56a8
Jul 02, 2020
- [X86] Enable multibyte NOPs in 64-bit mode for padding/alignment. · 0aad8294
  Craig Topper authored Jul 01, 2020
  0aad8294
- [X86-64] Support Intel AMX instructions · aded4f0c
  Xiang1 Zhang authored Jul 02, 2020
  aded4f0c
- Revert "[X86] Enable multibyte NOPs in 64-bit mode for padding/alignment." · c4207621
  Craig Topper authored Jul 01, 2020
  c4207621
Jul 01, 2020
- [X86] Enable multibyte NOPs in 64-bit mode for padding/alignment. · 3367e9da
  Craig Topper authored Jul 01, 2020
  3367e9da
Jun 20, 2020
- [X86] Correct the implementation of ud1(a.k.a. ud2b) instruction. · c721bc08
  Craig Topper authored Jun 19, 2020
  c721bc08
Jun 11, 2020
- [X86] Force VIA PadLock crypto instructions to emit a 0xF3 prefix when they... · 8fa3e8fa
  Craig Topper authored Jun 11, 2020
  8fa3e8fa
May 27, 2020
- [X86] Assemble movzb 1280(%rbx, %r12), %r12 after D80608 · 5b4cd2d4
  Fangrui Song authored May 27, 2020
  5b4cd2d4
- [X86][llvm-mc] Make the suffix matcher more accurate. · 6565b585
  Wang, Pengfei authored May 27, 2020
  6565b585
May 08, 2020
- [X86] Add assembler support for {vex} prefix to match GNU as. · adf3b8e3
  Craig Topper authored May 08, 2020
  adf3b8e3
May 06, 2020
- [X86] Remove support for Y0 constraint as an alias for Yz in inline assembly. · 16c800b8
  Craig Topper authored May 06, 2020
  16c800b8
Apr 27, 2020
- [llvm-objdump] Print target address with evaluateMemoryOperandAddress() · 3c9c9c17
  Fangrui Song authored Apr 23, 2020
  3c9c9c17
Apr 18, 2020
- [MC][X86] Disable branch align in non-text section · 0d3149f4
  Shengchen Kan authored Apr 18, 2020
  0d3149f4
Apr 16, 2020
- [MC][COFF][ELF] Reject instructions in IMAGE_SCN_CNT_UNINITIALIZED_DATA/SHT_NOBITS sections · e13a8a1f
  Fangrui Song authored Apr 14, 2020
  e13a8a1f
Apr 15, 2020
- [NFC][test] Mark the section which contains instructions executable · 22e919ca
  Shengchen Kan authored Apr 15, 2020
  22e919ca
Apr 11, 2020
- [NFC][test] Refine tests for branch align · 7ad46cfe
  Shengchen Kan authored Apr 11, 2020
  7ad46cfe
- [X86][MC] Make -x86-pad-max-prefix-size compatible with --mc-relax-all · 5d73f79c
  Shengchen Kan authored Apr 10, 2020
  5d73f79c
Apr 09, 2020
- Fix typo in comment · 9c7bd94c
  Jay Foad authored Apr 09, 2020
  
  9c7bd94c
- [X86] Add TSXLDTRK instructions. · a3dc9490
  WangTianQing authored Apr 09, 2020
  a3dc9490
Apr 08, 2020
- [X86][MC] Support enhanced relaxation for branch align · 916044d8
  Shengchen Kan authored Apr 07, 2020
  916044d8
Apr 02, 2020
- [X86] Add SERIALIZE instruction. · d08fadd6
  WangTianQing authored Apr 02, 2020
  d08fadd6
Apr 01, 2020
- [X86][MC] Disable Prefix padding after hardcode/prefix · d0efd7bf
  Shengchen Kan authored Mar 31, 2020
  d0efd7bf
Mar 27, 2020
- [MC][X86] Make .reloc support arbitrary relocation types · 152d14da
  Fangrui Song authored Mar 27, 2020
  152d14da
- [X86][MC] Fix the bug for prefix padding support · 1fb4f99a
  Shengchen Kan authored Mar 17, 2020
  1fb4f99a
Mar 26, 2020
- [X86InstPrinter] Change printPCRelImm to print the target address in hexadecimal form · 87de9a07
  Fangrui Song authored Mar 22, 2020
  87de9a07
Mar 17, 2020
- [MC] Recalculate fragment offsets after relaxation · 6a38e0e4
  Jian Cai authored Mar 12, 2020
  6a38e0e4
- [X86] Disable nop padding before instruction following hardcode · 39bcc76a
  Shengchen Kan authored Mar 13, 2020
  39bcc76a
- [Tests] Add test coverage for prefix selection logic · 5f777200
  Philip Reames authored Mar 16, 2020
  5f777200
Mar 16, 2020
- [NFC][X86] Simplify test cases for branch align · d2b522f1
  Shengchen Kan authored Mar 15, 2020
  
  d2b522f1
- Support prefix padding for alignment purposes (Relaxable instructions only) · a79863f2
  Philip Reames authored Mar 15, 2020
  a79863f2