Commits · f6e11a36c49c065cd71e9c54e4fba917da5bbf2e · Roger Ferrer / llvm-epi · GitLab

Oct 28, 2019
- [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLE · f6e11a36
  vhscampos authored Oct 17, 2019
  f6e11a36
- [AArch64][SVE] Implement masked load intrinsics · da720a38
  Kerry McLaughlin authored Oct 28, 2019
  da720a38
- [RISCV] Lower llvm.trap and llvm.debugtrap · 7214f7a7
  Sam Elliott authored Oct 28, 2019
  7214f7a7
- [X86] Fix 48/96 byte memcmp code gen · 657e4240
  David Zarzycki authored Oct 26, 2019
  657e4240
- [X86] Use 64-bit version of source register in LowerPATCHABLE_EVENT_CALL and... · 7af8d526
  Craig Topper authored Oct 27, 2019
  7af8d526
Oct 27, 2019
- [SDAG] fold insert_vector_elt with undef index · 85a2146c
  Sanjay Patel authored Oct 27, 2019
  85a2146c
- [LegalizeTypes] When promoting BITREVERSE/BSWAP don't take the shift amount... · f067dd83
  Craig Topper authored Oct 27, 2019
  f067dd83
Oct 26, 2019
- [X86] Prefer KORTEST on Knights Landing or later for memcmp() · 11c92020
  David Zarzycki authored Oct 17, 2019
  11c92020
- [X86] NFC: expand inline memcmp test coverage · 0d050938
  David Zarzycki authored Oct 20, 2019
  0d050938
- [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. · e921ede5
  cdevadas authored Oct 26, 2019
  e921ede5
- [SDAG] fold extract_vector_elt with undef index · 4c476176
  Sanjay Patel authored Oct 25, 2019
  4c476176
- [AMDGPU] Enable SGPR copy folding · 4c0251da
  Stanislav Mekhanoshin authored Oct 25, 2019
  4c0251da
Oct 25, 2019
- [BPF] fix a CO-RE issue with -mattr=+alu32 · a27c998c
  Yonghong Song authored Oct 24, 2019
  a27c998c
- [x86] add tests for extractelement with undef index (PR42689); NFC · e070cf81
  Sanjay Patel authored Oct 25, 2019
  
  e070cf81
- GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT · 1a276d1e
  Matt Arsenault authored Oct 01, 2019
  
  1a276d1e
- AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG · 171cf530
  Matt Arsenault authored Oct 08, 2019
  171cf530
- AMDGPU: Fix the broken dominator tree when creating waterfall loop for resource descriptor · 1ce552f3
  Changpeng Fang authored Oct 25, 2019
  1ce552f3
- Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." · 64c1f660
  Amy Huang authored Oct 25, 2019
  64c1f660
- [AMDGPU] Fold AGPR reg_sequence initializers · d4303b38
  Stanislav Mekhanoshin authored Oct 24, 2019
  d4303b38
- [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required) · c9c18e5a
  vpykhtin authored Oct 25, 2019
  c9c18e5a
- [DAGCombiner] widen zext of popcount based on target support · e6c145e0
  Sanjay Patel authored Oct 25, 2019
  e6c145e0
- AMDGPU/GlobalISel: Legalize FDIV16 · c35b358b
  Austin Kerbow authored Oct 22, 2019
  c35b358b
- [PowerPC] add test for popcnt with any_extend; NFC · b74d7e5c
  Sanjay Patel authored Oct 25, 2019
  b74d7e5c
- Add an instruction marker field to the ExtraInfo in MachineInstrs. · b85b4e5a
  Amy Huang authored Oct 16, 2019
  b85b4e5a
- [AMDGPU] Remove update_llc_test_checks for a test · 7ad3636c
  Scott Linder authored Oct 25, 2019
  7ad3636c
- [RISCV] Add support for half-precision floats · 1baa5039
  Luís Marques authored Oct 25, 2019
  1baa5039
- [MIPS GlobalISel] Select MSA vector generic and builtin fsqrt · 417dd678
  Petar Avramovic authored Oct 25, 2019
  417dd678
- [PowerPC] [Peephole] fold frame offset by using index form to save add. · 82205914
  czhengsz authored Oct 25, 2019
  82205914
- Test commit via git. · 81c2a5bb
  Kai Luo authored Oct 25, 2019
  
  81c2a5bb
Oct 24, 2019
- [AMDGPU] Clean up update_llc_test_checks CodeGen tests · 2c378339
  Scott Linder authored Oct 24, 2019
  2c378339
- [GlobalISel][AArch64][AMDGPU][X86] Teach LegalizationArtifactCombiner to combine trunc(g_constant). · a5376f63
  Craig Topper authored Oct 24, 2019
  a5376f63
- [AMDGPU] Fix mfma scheduling crash · 3c8e0551
  Stanislav Mekhanoshin authored Oct 24, 2019
  3c8e0551
- [InstCombine] Known-bits optimization for ARM MVE VADC. · e5f485c3
  Simon Tatham authored Sep 11, 2019
  e5f485c3
- [ARM] Add IR intrinsics for MVE VLD[24] and VST[24]. · e0ef4ebe
  Simon Tatham authored Oct 07, 2019
  e0ef4ebe
- [ARM] Add some sample IR MVE intrinsics with C++ isel. · ceeff95c
  Simon Tatham authored Oct 07, 2019
  ceeff95c
- [ARM] Begin adding IR intrinsics for MVE instructions. · 1b45297e
  Simon Tatham authored Oct 07, 2019
  1b45297e
- [AMDGPU] Skip additional folding on the same operand. · b2a65f0d
  Michael Liao authored Oct 23, 2019
  b2a65f0d
- [MIPS GlobalISel] Select MSA vector generic and builtin fabs · e3b49df5
  Petar Avramovic authored Oct 24, 2019
  e3b49df5
- [MIPS GlobalISel] MSA vector generic and builtin fadd, fsub, fmul, fdiv · 914ce664
  Petar Avramovic authored Oct 24, 2019
  914ce664
- [MIPS GlobalISel] MSA vector generic and builtin sdiv, srem, udiv, urem · 1d7f79c0
  Petar Avramovic authored Oct 24, 2019
  1d7f79c0