Commits · f81a8d03c109558b9d322c8864660532455ac3cf · Roger Ferrer / llvm-epi · GitLab

Mar 16, 2018
- [Hexagon] Avoid bank conflicts in post-RA scheduler · f81a8d03
  Krzysztof Parzyszek authored Mar 16, 2018
  f81a8d03
- [Hexagon] Add lit testcases for atomic intrinsics · 889cbcac
  Krzysztof Parzyszek authored Mar 16, 2018
  889cbcac
- [IR] Avoid the need to prefix MS C++ symbols with '\01' · f8b51c5f
  Reid Kleckner authored Mar 16, 2018
  f8b51c5f
- Revert r327721 "This patch fixes the invalid usage of OptSize in Machine Combiner." · 2aeb930a
  Reid Kleckner authored Mar 16, 2018
  2aeb930a
- [X86] Merge ADDSUB/SUBADD detection into single methods that can detect either... · f0815e01
  Craig Topper authored Mar 16, 2018
  f0815e01
- [CorrelatedValuePropagation] Use... · 71d69b2e
  Craig Topper authored Mar 16, 2018
  71d69b2e
- [AMDGPU] Supported ds_write_b128 generation. · c6c9dc87
  Farhana Aleen authored Mar 16, 2018
  c6c9dc87
- [X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits. · e6913ec3
  Craig Topper authored Mar 16, 2018
  e6913ec3
- [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes · 4c8f4234
  Dmitry Preobrazhensky authored Mar 16, 2018
  4c8f4234
- [LICM/mustexec] Extend first iteration must execute logic to fcmps · 8a106272
  Philip Reames authored Mar 16, 2018
  8a106272
- This patch fixes the invalid usage of OptSize in Machine Combiner. · a0cd09d4
  Andrew V. Tischenko authored Mar 16, 2018
  a0cd09d4
- [AMDGPU][MC] Corrected default values for unused SDWA operands · 9c1a6e7e
  Dmitry Preobrazhensky authored Mar 16, 2018
  9c1a6e7e
- [InstCombine] add nnan requirement to potential fabs folds tests; NFC · 2b94927f
  Sanjay Patel authored Mar 16, 2018
  2b94927f
- [SystemZ] Make AnyRegBitRegClass unallocatable. · a9f05a9d
  Jonas Paulsson authored Mar 16, 2018
  a9f05a9d
- [GISel]: Remove unused header include in MachineIRBuilder.h · 573102e3
  Aditya Nandakumar authored Mar 16, 2018
  573102e3
- [JumpThreading] Track unreachable BBs to avoid processing · f65ddc5f
  Brian M. Rzycki authored Mar 16, 2018
  f65ddc5f
- [Hexagon] Fix zero-extending non-HVX bool vectors · 9915291a
  Krzysztof Parzyszek authored Mar 16, 2018
  9915291a
- [ARM] Convert more invalid NEON immediate loads · ed1c8bfe
  Mikhail Maltsev authored Mar 16, 2018
  ed1c8bfe
- [X86][Btver2] Add correct mul/imul schedule costs · 23578e7d
  Simon Pilgrim authored Mar 16, 2018
  23578e7d
- [X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs · 8d28ae6a
  Simon Pilgrim authored Mar 16, 2018
  8d28ae6a
- [ARM] Fix a check in vmov/vmvn immediate parsing · 8dcf6fa3
  Mikhail Maltsev authored Mar 16, 2018
  8dcf6fa3
- [AArch64] Implement getArithmeticReductionCost · eacfefd0
  Matthew Simpson authored Mar 16, 2018
  eacfefd0
- HashTableTest: squelch some "comparison of integers of different signs" warnings · 3461b1e0
  Pavel Labath authored Mar 16, 2018
  3461b1e0
- DWARFVerifier: Enhance validation of .debug_names hash tables · 906b777a
  Pavel Labath authored Mar 16, 2018
  906b777a
- [TTI, AArch64] Allow the cost model analysis to test vector reduce intrinsics · 883e96c9
  Matthew Simpson authored Mar 16, 2018
  883e96c9
- [ARM] FP16 codegen support for VSEL · d391a1a9
  Sjoerd Meijer authored Mar 16, 2018
  d391a1a9
- [NFC] Void variables used for asserts only · 2e7fec7c
  Max Kazantsev authored Mar 16, 2018
  2e7fec7c
- [InstCombine] add more tests for fcmp+select -> fabs; NFC · 728269c1
  Sanjay Patel authored Mar 16, 2018
  728269c1
- [X86][Btver2] Add support for multiple pipelines stages for x86 scalar schedules. NFCI. · 14e5a1b0
  Simon Pilgrim authored Mar 15, 2018
  14e5a1b0
- [X86][Btver2] Tweak pipes test to remove register dependencies · 9c4157bb
  Simon Pilgrim authored Mar 15, 2018
  9c4157bb
- [SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a better job picking... · 1b8cf497
  Craig Topper authored Mar 15, 2018
  1b8cf497
- [X86][Btver2] Fix ymm div/sqrt to use fmul unit · 38948099
  Simon Pilgrim authored Mar 15, 2018
  38948099
Mar 15, 2018
- Use standard `print(dbgs())` pattern to implement DebugLoc::dump · 673f4b57
  Sean Silva authored Mar 15, 2018
  673f4b57
- [InstCombine] add tests for fcmp+select -> fabs; NFC · 2d568ec0
  Sanjay Patel authored Mar 15, 2018
  2d568ec0
- Fix PDB injected sources test. · a92e940a
  Zachary Turner authored Mar 15, 2018
  a92e940a
- [X86][Btver2] Add test to show timeline of fpu instructions on different pipes/units · 49a56fae
  Simon Pilgrim authored Mar 15, 2018
  49a56fae
- [PDB] Fix a bug where we were serializing hash tables incorrectly. · edbcbe0b
  Zachary Turner authored Mar 15, 2018
  edbcbe0b
- [WebAssembly] Add DebugLoc information to WebAssembly block and loop. · 10b31358
  Derek Schuff authored Mar 15, 2018
  10b31358
- [NVPTX] TblGen-ized lowering of WMMA intrinsics. · 7b14e7f0
  Artem Belevich authored Mar 15, 2018
  7b14e7f0
- [LoopUnroll] Peel off iterations if it makes conditions true/false. · fc97b617
  Florian Hahn authored Mar 15, 2018
  fc97b617