Commits · f84bc3793e9d1ba170a35b1909dd1057b63c2f15 · Roger Ferrer / llvm-epi · GitLab

May 05, 2018
- [globalisel] Update GlobalISel emitter to match new representation of extending loads · f84bc379
  Daniel Sanders authored May 05, 2018
  f84bc379
- [MIRPraser] Improve error checking for typed immediate operands · c86da6bc
  Heejin Ahn authored May 05, 2018
  c86da6bc
- [DAGCombiner] Masked merge: don't touch "not" xor's. · a3b0b59f
  Roman Lebedev authored May 05, 2018
  a3b0b59f
- [CaptureTracking] Handle capturing of launder.invariant.group · e9832dfd
  Piotr Padlewski authored May 05, 2018
  e9832dfd
- [MIRParser] Allow register class names in the form of integer/scalar · c2ad0968
  Heejin Ahn authored May 05, 2018
  c2ad0968
- [LTO] Allow pass remarks with hotness to be set when emitting to stderr · b77ab096
  Teresa Johnson authored May 04, 2018
  b77ab096
- Mapping SDNode flags to MachineInstr flags · 2dcf12ff
  Michael Berg authored May 04, 2018
  2dcf12ff
May 04, 2018
- [LICM] Compute a must execute property for the prefix of the header as we go · 5b39acd1
  Philip Reames authored May 04, 2018
  5b39acd1
- AMDGPU: Add D16 instructions preserve unused bits feature · c2c2eb7d
  Konstantin Zhuravlyov authored May 04, 2018
  c2c2eb7d
- [MachineLICM] Debug intrinsics shouldn't affect hoist decisions · 8e4958e7
  Geoff Berry authored May 04, 2018
  8e4958e7
- [ObjCARC] Account for catchswitch in bitcast insertion · 57fadab1
  Shoaib Meenai authored May 04, 2018
  57fadab1
- Fast Math Flag mapping into SDNode · 7acc81b7
  Michael Berg authored May 04, 2018
  7acc81b7
- [X86] Add WriteEMMS scheduler class · 0e51a125
  Simon Pilgrim authored May 04, 2018
  0e51a125
- [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides. · d7ffbc5c
  Simon Pilgrim authored May 04, 2018
  d7ffbc5c
- [AArch64] Add missing testcase for r331522 · 6d56294c
  Adhemerval Zanella authored May 04, 2018
  6d56294c
- obj2yaml: Correctly round-trip default alignment. · 9096413f
  Peter Collingbourne authored May 04, 2018
  9096413f
- DwarfCompileUnit: Fix another assertion failure on malformed input · 3edc63a5
  Adrian Prantl authored May 04, 2018
  3edc63a5
- [Hexagon] Handle non-immediate constants in HexagonSplitDouble · effcc2fb
  Krzysztof Parzyszek authored May 04, 2018
  effcc2fb
- [mips] Correct the predicates of sign extension instructions · 65b0492f
  Simon Dardis authored May 04, 2018
  65b0492f
- [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32 · a57ef17a
  Adhemerval Zanella authored May 04, 2018
  a57ef17a
- [Hexagon] Skip reserved physical registers when updating liveness · af73d2bd
  Krzysztof Parzyszek authored May 04, 2018
  af73d2bd
- [X86] Add SchedWriteFRnd fp rounding scheduler classes · be51b201
  Simon Pilgrim authored May 04, 2018
  be51b201
- [X86] Add test case for PR30290s failing behaviour · 07e8daa6
  Jeremy Morse authored May 04, 2018
  07e8daa6
- Word wrap a test-file comment to 80 columns · 71f17bf8
  Jeremy Morse authored May 04, 2018
  71f17bf8
- [RegUsageInfoCollector] Bugfix for handling of register aliases. · 72fe7605
  Jonas Paulsson authored May 04, 2018
  72fe7605
- [LoopIdiomRecognize] Add a test case to show incorrect transformation of an... · a3f39ee3
  Craig Topper authored May 03, 2018
  a3f39ee3
- [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes · 0aed7315
  Simon Pilgrim authored May 03, 2018
  0aed7315
May 03, 2018
- [InstCombine] refine select-of-constants to bitwise ops · e7b66547
  Sanjay Patel authored May 03, 2018
  e7b66547
- [ThinLTO] Add support for optimization remarks to thinBackend · 85cc298c
  Teresa Johnson authored May 03, 2018
  85cc298c
- [PowerPC] add more FMF debug output; NFC · 52151885
  Sanjay Patel authored May 03, 2018
  52151885
- [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes · f2d2ceda
  Simon Pilgrim authored May 03, 2018
  f2d2ceda
- [PowerPC] add tests for FMF propagation; NFC · e7532d29
  Sanjay Patel authored May 03, 2018
  e7532d29
- Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)" · 304877e5
  Bjorn Pettersson authored May 03, 2018
  304877e5
- [CodeGen][X86][NFC] Copy two selectcc tests from AArch64. · 63ac1936
  Roman Lebedev authored May 03, 2018
  63ac1936
- [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes · f7dd6069
  Simon Pilgrim authored May 03, 2018
  f7dd6069
- ARM: don't try to over-align large vectors as arguments. · 28e0a6f7
  Tim Northover authored May 03, 2018
  28e0a6f7
- perform DSE through launder.invariant.group · c77ab8ef
  Piotr Padlewski authored May 03, 2018
  c77ab8ef
- Rename invariant.group.barrier to launder.invariant.group · 5dde8094
  Piotr Padlewski authored May 03, 2018
  5dde8094
- [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and... · 93c878c7
  Simon Pilgrim authored May 03, 2018
  93c878c7
- [WebAssembly] MC: Don't litter test directory. · 281919f5
  Benjamin Kramer authored May 03, 2018
  281919f5