Commits · faad1b3056f6fa17898b02e0502cd072bcac023d · Roger Ferrer / llvm-epi · GitLab

Oct 05, 2018
- [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() · faad1b30
  Jonas Paulsson authored Oct 05, 2018
  faad1b30
- Add missing period to comment to match style of file. · d2261f61
  Neil Henning authored Oct 05, 2018
  d2261f61
- AMDGPU/GlobalISel: Add support for G_INTTOPTR · 7c65078f
  Tom Stellard authored Oct 05, 2018
  7c65078f
- [WebAssembly] Saturating arithmetic intrinsics · 4b47d08e
  Thomas Lively authored Oct 05, 2018
  4b47d08e
- [WebAssembly] Fixed missing "global" symbol type in AsmParser. · 15a50e2c
  Wouter van Oortmerssen authored Oct 04, 2018
  15a50e2c
- [globalisel][combine] When placing truncates, handle the case when the BB is empty · a464ffd5
  Daniel Sanders authored Oct 04, 2018
  a464ffd5
- [SimplifyCFG] Pass AggressiveInsts to DominatesMergePoint by reference. Remove null check. · 029d1ef6
  Craig Topper authored Oct 04, 2018
  029d1ef6
- [WebAssembly] Ignore DBG_VALUE in WebAssemblyCFGStackify pass when looking for block start · 409b4391
  Yury Delendik authored Oct 04, 2018
  409b4391
Oct 04, 2018
- [RISCV] Support named operands for CSR instructions. · 9d6c5532
  Ana Pazos authored Oct 04, 2018
  9d6c5532
- [globalisel][combine] Fix a rare crash when encountering an instruction whose op0 isn't a reg · ab358bfd
  Daniel Sanders authored Oct 04, 2018
  ab358bfd
- [InstCombine] drop poison flags in SimplifyVectorDemandedElts · 3436dc29
  Sanjay Patel authored Oct 04, 2018
  3436dc29
- [X86][LegalizeVectorOps] Use MERGE_VALUES to return two results from... · 7d2155e3
  Craig Topper authored Oct 04, 2018
  7d2155e3
- [SimplifyCFG] Change recursive calls to llvm::SimplifyCFG to instead use an... · 1d15f7b0
  Craig Topper authored Oct 04, 2018
  1d15f7b0
- [WebAssembly] Don't modify preds/succs iterators while erasing from them · b68d5914
  Heejin Ahn authored Oct 04, 2018
  b68d5914
- AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa · aa067cb9
  Konstantin Zhuravlyov authored Oct 04, 2018
  aa067cb9
- [COFF] [X86] Don't use llvm_unreachable for unsupported relocation types · 37b742e2
  Martin Storsjö authored Oct 04, 2018
  37b742e2
- [InstCombine] reduce code duplication in SimplifyDemandedVectorElts; NFCI · 9d6688e3
  Sanjay Patel authored Oct 04, 2018
  9d6688e3
- Give same-named members unique timestamps on Darwin in llvm-ar. · 0d1bb79a
  James Y Knight authored Oct 04, 2018
  0d1bb79a
- [globalisel][combine] Improve the truncate placement for the extending-loads combine · a05c7583
  Daniel Sanders authored Oct 04, 2018
  a05c7583
- AArch64: Fix XSeqPairs/WSeqPairs problems · 0c67a4e9
  Matthias Braun authored Oct 04, 2018
  0c67a4e9
- [AMDGPU] Match signed dot4/8 pattern. · 4bc597bf
  Farhana Aleen authored Oct 04, 2018
  4bc597bf
- [InstCombine] allow bitcast to/from FP for vector insert/extract transform · 3746e11a
  Sanjay Patel authored Oct 04, 2018
  3746e11a
- [RISCV] Remove overzealous is64Bit checks · 5bf3b20e
  Alex Bradbury authored Oct 04, 2018
  5bf3b20e
- [X86] Set correct MMO offset on scalarized load pieces · 4f916df2
  David Greene authored Oct 04, 2018
  4f916df2
- [PassTimingInfo] cleanup on TimingData's Timer handling · eb20c307
  Fedor Sergeev authored Oct 04, 2018
  eb20c307
- Fix MSVC "not all control paths return a value" warning. NFCI. · 991b0d24
  Simon Pilgrim authored Oct 04, 2018
  991b0d24
- [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F · e96b7c88
  Alex Bradbury authored Oct 04, 2018
  e96b7c88
- [X86] Merge matchANDXORWithAllOnesAsANDNP into combineANDXORWithAllOnesIntoANDNP. NFCI · 8b3c46f0
  Craig Topper authored Oct 04, 2018
  8b3c46f0
- [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR} · 0e16766b
  Alex Bradbury authored Oct 04, 2018
  0e16766b
- [LegalizeIntegerTypes] Fix typo in comment. NFC · 08ae6774
  Craig Topper authored Oct 04, 2018
  08ae6774
- [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine · 5ac0a2fc
  Alex Bradbury authored Oct 03, 2018
  5ac0a2fc
- [WebAssembly] Bitselect intrinsic and instruction · 5d461c96
  Thomas Lively authored Oct 03, 2018
  5d461c96
- [RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLowering · 1dbfdeb6
  Alex Bradbury authored Oct 03, 2018
  1dbfdeb6
- [WebAssembly] Refactor WasmSignature and use it for MCSymbolWasm · 77a7a380
  Derek Schuff authored Oct 03, 2018
  77a7a380
- [machineverifier] Detect PHI's that are preceeded by non-PHI's · 1b493739
  Daniel Sanders authored Oct 03, 2018
  1b493739
Oct 03, 2018
- [InstCombine] allow SimplifyDemandedVectorElts to work with FP binops · cafdeb1a
  Sanjay Patel authored Oct 03, 2018
  cafdeb1a
- Make meanings of variables clearer in action table generation (NFC) · 9d224346
  Heejin Ahn authored Oct 03, 2018
  9d224346
- [X86] Stop promoting vector ISD::SELECT to vXi64. · a65c2dbf
  Craig Topper authored Oct 03, 2018
  a65c2dbf
- [X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1 SELECT into v8i1. · c39dc41b
  Craig Topper authored Oct 03, 2018
  c39dc41b
- [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection · ce904995
  Alex Bradbury authored Oct 03, 2018
  ce904995