Commits · fae05692a36f9ebbd201d93c2a6b0f927564d7e6 · Roger Ferrer / llvm-epi · GitLab

Jun 30, 2021
- CodeGen: Print/parse LLTs in MachineMemOperands · fae05692
  Matt Arsenault authored May 19, 2021
  fae05692
- [GISel] Support llvm.memcpy.inline · a6428724
  Jon Roelofs authored Jun 29, 2021
  a6428724
- [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants · 381ded34
  Stanislav Mekhanoshin authored Jun 28, 2021
  381ded34
- [ARM] Set the immediate cost of GEP operands to 0 · cd76f43b
  David Green authored Jun 30, 2021
  cd76f43b
- [AIX][XCOFF][BUG-Fixed] need to switch back to text section after emit a dumy eh structure · 9a9e6189
  zhijian authored Jun 30, 2021
  9a9e6189
- [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce... · 59fa435e
  Simon Pilgrim authored Jun 30, 2021
  59fa435e
- [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address · 00291150
  Bradley Smith authored Jun 28, 2021
  00291150
- [ARMInstPrinter] Print the target address of a branch instruction · 657e067b
  Igor Kudrin authored Jun 30, 2021
  657e067b
- Recommit "[AArch64] Custom lower <4 x i8> loads" · b062fff8
  Sjoerd Meijer authored Jun 29, 2021
  b062fff8
- [PowerPC][AIX] Re-generate test aix-framepointer-save-restore.ll. NFC. · 1f169a77
  Kai Luo authored Jun 30, 2021
  
  1f169a77
- [PowerPC][AIX] Pre-commit tracetable test for D100167. NFC. · 338a3f49
  Kai Luo authored Jun 30, 2021
  
  338a3f49
- [AMDGPU] Update gfx90a memory model support · 7f19aa73
  Tony Tye authored May 07, 2021
  7f19aa73
- [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX 6.5 and 7.0 WMMA and MMA instructions · 3644726a
  Steffen Larsen authored Jun 28, 2021
  3644726a
Jun 29, 2021
- CodeGen: Store LLT instead of uint64_t in MachineMemOperand · 990278d0
  Matt Arsenault authored May 19, 2021
  990278d0
- [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines · a9854045
  Fangrui Song authored Jun 29, 2021
  a9854045
- [OpaquePtr] Support forward references in textual IR · f8aaec19
  Nikita Popov authored Jun 25, 2021
  f8aaec19
- [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization... · 91322998
  Craig Topper authored Jun 29, 2021
  91322998
- [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being... · 3b6dfa38
  Craig Topper authored Jun 28, 2021
  3b6dfa38
- [AMDGPU] Fix 224-bit spills · f38a8b54
  Piotr Sobczak authored Jun 29, 2021
  f38a8b54
- [ARM] Extra test for gep immediate costs. NFC · aaf6a7ac
  David Green authored Jun 29, 2021
  
  aaf6a7ac
- [SVE] Added CodeGen support for inserting an element into a predicate vector · c3d3defd
  Dylan Fleming authored Jun 29, 2021
  c3d3defd
- [AVR] Fix a bug in prologue of ISR · c85175c5
  Ben Shi authored Jun 29, 2021
  c85175c5
- [X86] Add cmov i33 sgt test case · f0d6c915
  Simon Pilgrim authored Jun 29, 2021
  f0d6c915
- [ARM] Fold extract of ARM_BUILD_VECTOR · 371ee32e
  David Green authored Jun 29, 2021
  371ee32e
- [X86] Add a test to reveal a bug in CMOV conversion. · 6178ddcd
  Tianqing Wang authored Jun 29, 2021
  6178ddcd
- [MIRParser] Add machine metadata. · e818efac
  Michael Liao authored May 25, 2021
  e818efac
Jun 28, 2021
- [Hexagon] Add patterns to load i1 · 9c5ed8d5
  Krzysztof Parzyszek authored Jun 25, 2021
  9c5ed8d5
- Revert "[AArch64] Custom lower <4 x i8> loads" · 3a7cea28
  Sjoerd Meijer authored Jun 28, 2021
  3a7cea28
- [AArch64] Added tests to neon-truncstore.ll. NFC. · 7bcb3bd1
  Sjoerd Meijer authored Jun 25, 2021
  
  7bcb3bd1
- [llvm][clang][fpenv] Create new intrinsic llvm.arith.fence to control FP... · 931e9568
  Melanie Blower authored Jun 07, 2021
  931e9568
- Teach peephole optimizer to not emit sub-register defs · 31ef15e0
  Ahsan Saghir authored May 31, 2021
  31ef15e0
- [AArch64][SVE] DAG combine SETCC_MERGE_ZERO of a SETCC_MERGE_ZERO · c089e29a
  Bradley Smith authored Jun 25, 2021
  c089e29a
- [AVR][test] Add a new test: functions with struct return type · 1dd2d15b
  Ben Shi authored Jun 28, 2021
  1dd2d15b
- [AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX · f9f5d415
  Brendon Cahoon authored Apr 30, 2021
  f9f5d415
- [NFC] Adding test for clobbering of high registers in Thumb · 7749b19e
  Lucas Prates authored Feb 09, 2021
  7749b19e
- [ARM] Add an extra fold for f32 extract(vdup(i32)) · a1c0f09a
  David Green authored Jun 28, 2021
  a1c0f09a
- Revert "[M68k][GloballSel] Formal arguments lowering in IRTranslator" · 04242bdc
  Min Hsu authored Jun 27, 2021
  04242bdc
- [M68k][GloballSel] Formal arguments lowering in IRTranslator · 8f43407a
  Sushma Unnibhavi authored Jun 27, 2021
  8f43407a
Jun 27, 2021
- [RISCV] Add tests for __builtin_parity idiom. · 4c92e31d
  Craig Topper authored Jun 27, 2021
  4c92e31d
- Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve... · 010f0f00
  Craig Topper authored Jun 27, 2021
  010f0f00