Commits · fb10aff542f67a0717e2d3185fb600aba20e06c7 · Roger Ferrer / llvm-epi · GitLab

Jan 27, 2018
- Regenerate test result for stateppint-vector.ll. NFC. · fb10aff5
  Amaury Sechet authored Jan 27, 2018
  fb10aff5
- Regenrate brcond.ll test results. NFC · c2072434
  Amaury Sechet authored Jan 27, 2018
  c2072434
- Regenrate test results for avx-brcond.ll . NFC · a078c2e5
  Amaury Sechet authored Jan 27, 2018
  a078c2e5
- [X86][SSE] Regenerate fp2int/int2fp tests · a01a5243
  Simon Pilgrim authored Jan 27, 2018
  a01a5243
- Regenerate test results for and-su.ll . NFC · 1ae296da
  Amaury Sechet authored Jan 27, 2018
  1ae296da
- [X86][SSE] Add broadcast from v2i32 memory tests (PR34394) · 516cee12
  Simon Pilgrim authored Jan 27, 2018
  516cee12
- [TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of vXi1... · 2c570eaa
  Craig Topper authored Jan 27, 2018
  2c570eaa
- [SelectionDAG] Make DAGTypeLegalizer::PromoteSetCCOperands handle SETEQ/SETNE... · c80f0ced
  Craig Topper authored Jan 27, 2018
  c80f0ced
- [GlobalISel][Legalizer] Convert the FP constants to the right APFloat type for G_FCONSTANT. · 77a5c965
  Amara Emerson authored Jan 27, 2018
  77a5c965
Jan 26, 2018
- [X86] Use vpternlog to implement vector not under AVX512. · 8a444ee6
  Craig Topper authored Jan 26, 2018
  8a444ee6
- [Hexagon] Generate constant splats instead of loads from constant pool · 90ca4e8b
  Krzysztof Parzyszek authored Jan 26, 2018
  90ca4e8b
- [Hexagon] Make sure that offset on globals matches alignment requirements · d4273abb
  Krzysztof Parzyszek authored Jan 26, 2018
  d4273abb
- [Hexagon] Replace multiple vector extracts with store-load combinations · 95614acc
  Krzysztof Parzyszek authored Jan 26, 2018
  95614acc
- [LivePhysRegs] Preserve pristine regs in blocks with no successors. · 29108843
  Eli Friedman authored Jan 26, 2018
  29108843
- [X86] Allow any_extend to be combined with setcc on VLX targets. · d4795b70
  Craig Topper authored Jan 26, 2018
  d4795b70
- [X86][AVX512] Add combining support for X86ISD::VTRUNCS · 8e9becbd
  Simon Pilgrim authored Jan 26, 2018
  8e9becbd
- [Hexagon] Fix an incorrect assertion in HexagonConstExtenders · 1a1edbfb
  Krzysztof Parzyszek authored Jan 26, 2018
  1a1edbfb
- [X86][AVX] LowerBUILD_VECTORAsVariablePermute - add support for VPERMILPV to v4i32/v4f32 · 1b14bdc0
  Simon Pilgrim authored Jan 26, 2018
  1b14bdc0
- [X86][SSE] Don't colaesce v4i32 extracts · 76ede609
  Simon Pilgrim authored Jan 26, 2018
  76ede609
- [DAG] Teach findBaseOffset to interpret indexes of indexed memory operations · 9896238d
  Nirav Dave authored Jan 26, 2018
  9896238d
- [MIPS] Don't crash on unsized extern types with -mgpopt · 1f9636f3
  Alexander Richardson authored Jan 26, 2018
  1f9636f3
- [DAGCombine] reduceBuildVecToShuffle - ensure EXTRACT_VECTOR_ELT index is in range · f531cf89
  Simon Pilgrim authored Jan 26, 2018
  f531cf89
- [X86][SSE] Add tests for vector truncation with PACKUS style signed saturation · 65ec9238
  Simon Pilgrim authored Jan 26, 2018
  65ec9238
- [MIR] Add support for addrspace in MIR · e4718e84
  Francis Visoiu Mistrih authored Jan 26, 2018
  e4718e84
- [AMDGPU] fix LDS f32 intrinsics · 6e1dc681
  Daniil Fukalov authored Jan 26, 2018
  6e1dc681
- [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative · d2cc6fd9
  Momchil Velikov authored Jan 26, 2018
  d2cc6fd9
- [X86FixupBWInsts] Prefer positive checks in the test. NFC · cbc5a688
  Andrei Elovikov authored Jan 26, 2018
  cbc5a688
- [ARM] Armv8.2-A FP16 code generation (part 1/3) · 011de9c0
  Sjoerd Meijer authored Jan 26, 2018
  011de9c0
- [NFC] fix trivial typos in comments and documents · 0909ca13
  Hiroshi Inoue authored Jan 26, 2018
  0909ca13
- [CGP] Re-enable Select in complex addressing mode. · 9fe0524e
  Serguei Katkov authored Jan 26, 2018
  9fe0524e
- [X86] Fix killed flag handling in X86FixupLea pass · 1ce7137c
  Serguei Katkov authored Jan 26, 2018
  1ce7137c
- [CodeGen] Ignore private symbols in llvm.used for COFF · d8fd16b0
  Shoaib Meenai authored Jan 26, 2018
  d8fd16b0
Jan 25, 2018
- [Hexagon] SETEQ and SETNE are valid integer condition codes · b2c458e6
  Krzysztof Parzyszek authored Jan 25, 2018
  b2c458e6
- [X86][SSE] Add tests for vector truncation with signed saturation · fb01d066
  Simon Pilgrim authored Jan 25, 2018
  fb01d066
- [X86][SSE] Add tests for vector truncation with unsigned saturation · e59bf81e
  Simon Pilgrim authored Jan 25, 2018
  e59bf81e
- X86 Tests: Add AVX+XOP config to SDIV combine tests · 0fb9638e
  Zvi Rackover authored Jan 25, 2018
  0fb9638e
- [X86] Expand IMUL/MUL instregexs in Intel scheduler models. Add load latency... · b369cdba
  Craig Topper authored Jan 25, 2018
  b369cdba
Jan 24, 2018
- [GlobalISel] Add a requires: asserts to a test. · 5ee03988
  Amara Emerson authored Jan 24, 2018
  5ee03988
- [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. · 4f84f886
  Amara Emerson authored Jan 24, 2018
  4f84f886
- [GlobalISel] Don't fall back to FastISel. · f386e2b0
  Amara Emerson authored Jan 24, 2018
  f386e2b0